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? freescale semiconductor, inc., 2009. all rights reserved. freescale semiconductor technical data 1overview the mpc8640 processor family integrates either one or two power architecture? e600 processor cores with system logic required for networking, storage, wireless infrastructure, and general- purpose embedded applications. the mpc8640 integrates one e600 core while the mpc8640d integrates two cores. this section provides a high-level overview of the mpc8640 and mpc8640d features. when referring to the mpc8640 throughout the document, the functionality described applies to both the mpc8640 and the mpc8640d. any differences specific to the mpc8640d are noted. figure 1 shows the major functional units within the mpc8640 and mpc8640d. the major difference between the mpc8640 and mpc8640d is that there are two cores on the mpc8640d. contents 1. overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2. electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 6 3. power characteristics . . . . . . . . . . . . . . . . . . . . . . . . 13 4. input clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5. reset initialization . . . . . . . . . . . . . . . . . . . . . . . . . 18 6. ddr and ddr2 sdram . . . . . . . . . . . . . . . . . . . . . 19 7. duart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8. ethernet: enhanced three-speed ethernet (etsec), mii management . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 9. ethernet management interface electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 10. local bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 11. jtag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 12. i 2 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 13. high-speed serial interfaces (hssi) . . . . . . . . . . . . 57 14. pci express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 15. serial rapidio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 16. package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 17. signal listings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 18. clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 19. thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 20. system design information . . . . . . . . . . . . . . . . . . 116 21. ordering information . . . . . . . . . . . . . . . . . . . . . . . 126 22. document revision history . . . . . . . . . . . . . . . . . . 128 mpc8640 and mpc8640d integrated host processor hardware specifications document number: mpc8640dec rev. 3, 07/2009
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 2 freescale semiconductor overview figure 1. mpc8640 and mpc8640d and 1x/4x srio (2.5 gb/s) ] [ x1/x2/x4/x8 pci exp (4 gb/s) or [2-x1/x2/x4/x8 pci express (8 gb/s) ] 32-kbyte l1 instruction cache e600 core 32-kbyte l1 data cache e600 core block local bus controller multiprocessor programmable interrupt ddr sdram controller sdram irqs external control ddr sdram controller (lbc) controller (mpic) sdram rom, gpio dual universal asynchronous receiver/transmitter (duart) serial i 2 c controller i 2 c i 2 c controller i 2 c enhanced tsec controller 10/100/1gb enhanced tsec controller 10/100/1gb enhanced tsec controller 10/100/1gb pci express interface four-channel dma controller enhanced tsec controller 10/100/1gb ocean switch fabric mpx coherency module (mcm) 1-mbyte l2 cache platform mpx bus rmii, gmii, mii, rgmii, tbi, rtbi rmii, gmii, mii, rgmii, tbi, rtbi rmii, gmii, mii, rgmii, tbi, rtbi rmii, gmii, mii, rgmii, tbi, rtbi platform bus e600 core e600 core block l2 cache 32-kbyte l1 instruction cache 32-kbyte l1 data cache 1-mbyte serial rapidio interface or pci express interface
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 freescale semiconductor 3 overview 1.1 key features the following lists the mpc8640 key feature set: ? major features of the e600 core are as follows: ? high-performance, 32-bit superscalar mic roprocessor that implements the powerpc instruction set architecture (isa) ? eleven independent execution uni ts and three register files ? branch processing unit (bpu) ? four integer units (ius) that share 32 gprs for integer operands ? 64-bit floating-point unit (fpu) ? four vector units and a 32-entry vector register file (vrs) ? three-stage load/store unit (lsu) ? three issue queues, fiq, viq, and giq, can accept as many as one, two, and three instructions, respectively, in a cycle. ? rename buffers ? dispatch unit ? completion unit ? two separate 32-kbyte instructi on and data level 1 (l1) caches ? integrated 1-mbyte, eight-way set-associative uni fied instruction and data level 2 (l2) cache with ecc ? 36-bit real addressing ? separate memory management units (mmus) for instructions and data ? multiprocessing support features ? power and thermal management ? performance monitor ? in-system testability and debugging features ? reliability and serviceability ? mpx coherency module (mcm) ? ten local address windows plus two default windows ? optional low memory offset mode for core 1 to allow for address disambiguation ? address translation and mapping units (atmus) ? eight local access windows define mapping within local 36-bit address space ? inbound and outbound atmus map to larger external address spaces ? three inbound windows plus a configuration window on pci express? interface unit ? four inbound windows plus a default window on serial rapidio interface unit ? four outbound windows plus default translation for pci express interface unit ? eight outbound windows plus default translation for serial rapidio? interface unit with segmentation and subsegmentation support
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 4 freescale semiconductor overview ? ddr memory controllers ? dual 64-bit memory controllers (72-bit with ecc) ? support of up to a 266 mhz clock rate and a 533 mhz ddr2 sdram ? support for ddr, ddr2 sdram ? up to 16 gbytes per memory controller ? cache line and page interleaving between memory controllers. ? serial rapidio interface unit ? supports rapidio interconnect specification , revision 1.2 ? both 1 and 4 lp-serial link interfaces ? transmission rates of 1.25-, 2.5-, and 3.125-gbaud (data rates of 1.0-, 2.0-, and 2.5-gbps) per lane ? message unit compliant with rapidio specifications ? rapidio atomic transactions to the memory controller ? pci express interface ? pci express 1.0a compatible ? supports 1, 2, 4, and 8 link widths ? 2.5 gbaud, 2.0 gbps lane ? four enhanced three-speed ethernet controllers (etsecs) ? three-speed support (10/100/1000 mbps) ? four controllers that comply with ieee std. 802.3?, 802.3u?, 802.3x?, 802.3z?, 802.3ac?, 802.3ab? standards ? support for the following physical interfaces: mii, rmii, gmii, rgmii, tbi, and rtbi ? support for a full-duplex fifo mode for high-efficiency asic connectivity ? tcp/ip off-load ? header parsing ? quality of service support ? vlan insertion and deletion ? mac address recognition ? buffer descriptors are backward compatible with powerquicc ii and powerquicc iii programming models ? rmon statistics support ? mii management interface for control and status ? programmable interrupt controller (pic) ? programming model is compliant with the openpic architecture ? supports 16 programmable interrupt a nd processor task priority levels ? supports 12 discrete external interrupts and 48 internal interrupts ? eight global high resolution timers/counters that can generate interrupts
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 freescale semiconductor 5 overview ? allows processors to interrupt each other with 32b messages ? support for pci-express message-shared interrupts (msis) ? local bus controller (lbc) ? multiplexed 32-bit address and data operating at up to 125 mhz ? eight chip selects support eight external slaves ? integrated dma controller ? four-channel controller ? all channels accessible by both the local and the remote masters ? supports transfers to or from any local memory or i/o port ? ability to start and flow control each dma channel from external 3-pin interface ? device performance monitor ? supports eight 32-bit counters that count the occurrence of selected events ? ability to count up to 512 counter-specific events ? supports 64 reference events that can be counted on any of the 8 counters ? supports duration and quantity threshold counting ? burstiness feature that permits counting of burst events with a programmable time between bursts ? triggering and chaining capability ? ability to generate an interrupt on overflow ? dual i 2 c controllers ? two-wire interface ? multiple master support ? master or slave i 2 c mode support ? on-chip digital filtering rejects spikes on the bus ? boot sequencer ? optionally loads configuration data from serial rom at reset via the i 2 c interface ? can be used to initialize configuration registers and/or memory ? supports extended i 2 c addressing mode ? data integrity checked with preamble signature and crc ? duart ? two 4-wire interfaces (sin, sout, rts , cts ) ? programming model compatible with the original 16450 uart and the pc16550d ? ieee 1149.1?-compliant, jtag boundary scan ? available as 1023 pin hi-cte flip chip ceramic ball grid array (fc-cbga)
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 6 freescale semiconductor electrical characteristics 2 electrical characteristics this section provides the ac and dc electrical specifications and thermal characteristics for the mpc8640. the mpc8640 is currently targeted to these specifications. 2.1 overall dc electrical characteristics this section covers the ratings, conditions, and other characteristics. 2.1.1 absolute maximum ratings table 1 provides the absolute maximum ratings. table 1. absolute maximum ratings 1 parameter symbol absolute maximum value unit notes cores supply voltages v dd _core0, v dd _core1 ?0.3 to 1.21 v v 2 cores pll supply av dd _core0, av dd _core1 ?0.3 to 1.21 v v ? serdes transceiver supply (ports 1 and 2) sv dd ?0.3 to 1.21 v v ? serdes serial i/o supply port 1 xv dd_ srds1 ?0.3 to 1.21 v v ? serdes serial i/o supply port 2 xv dd_ srds2 ?0.3 to 1.21 v v ? serdes dll and pll supply voltage for port 1 and port 2 av dd _srds1, av dd _srds2 ?0.3 to 1.21v v ? platform supply voltage v dd _plat ?0.3 to 1.21v v ? local bus and platform pll supply voltage av dd _lb, av dd _plat ?0.3 to 1.21v v ? ddr and ddr2 sdram i/o supply voltages d1_gv dd, d2_gv dd ?0.3 to 2.75 v v 3 ?0.3 to 1.98 v v 3 etsec 1 and 2 i/o supply voltage lv dd ?0.3 to 3.63 v v 4 ?0.3 to 2.75 v v 4 etsec 3 and 4 i/o supply voltage tv dd ?0.3 to 3.63 v v 4 ?0.3 to 2.75 v v 4 local bus, duart, dma, multiprocessor interrupts, system control & clocking, debug, test, power management, i 2 c, jtag and miscellaneous i/o voltage ov dd ?0.3 to 3.63v v ?
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 freescale semiconductor 7 electrical characteristics 2.1.2 recommended operating conditions table 2 provides the recommended operating conditions for the mpc8640. note that the values in table 2 are the recommended and tested operating conditions. proper device operation outside of these conditions is not guaranteed. for details on order information and specific operating conditions for parts, see section 21, ?ordering information.? input voltage ddr and ddr2 sdram signals d n _ mv in ?0.3 to (d n _gv dd + 0.3) v 5 ddr and ddr2 sdram reference d n _ mv ref ?0.3 to (d n _gv dd 2 + 0.3) v? three-speed ethernet signals lv in tv in gnd to (lv dd + 0.3) gnd to (tv dd + 0.3) v 5 duart, local bus, dma, multiprocessor interrupts, system control and clocking, debug, test, power management, i 2 c, jtag and miscellaneous i/o voltage ov in gnd to (ov dd + 0.3) v 5 storage temperature range t stg ?55 to 150 o c? notes: 1. functional and tested operating conditions are given in ta b l e 2 . absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. stresses beyond those listed may affect device reliability or cause permanent damage to the device. 2. core 1 characteristics apply only to mpc8640d. if two separate power supplies are used for v dd _core0 and v dd _core1, they must be kept within 100 mv of each other during normal run time. 3. the ?0.3 to 2.75 v range is for ddr and ?0.3 to 1.98 v range is for ddr2. 4. the 3.63 v maximum is only supported when the port is configured in gmii, mii, rmii, or tbi modes; otherwise the 2.75 v maximum applies. see section 8.2, ?fifo, gmii, mii, tbi, rgmii, rmii, and rtbi ac timing specifications ,? for details on the recommended operating conditions per protocol. 5. during run time (m,l,t,o)v in and d n _mv ref may overshoot/undershoot to a voltage and for a maximum duration as shown in figure 2 . table 2. recommended operating conditions parameter symbol recommended value unit notes cores supply voltages v dd _core0, v dd _core1 1.05 50 mv v 1, 2 0.95 50 mv 1, 2, 10 cores pll supply av dd _core0, av dd _core1 1.05 50 mv v 11 0.95 50 mv 10, 11 serdes transceiver supply (ports 1 and 2) sv dd 1.05 50 mv v 9 serdes serial i/o supply port 1 xv dd_ srds1 1.05 50 mv v ? serdes serial i/o supply port 2 xv dd_ srds2 1.05 50 mv v ? serdes dll and pll supply voltage for port 1 and port 2 av dd _srds1, av dd _srds2 1.05 50 mv v ? table 1. absolute maximum ratings 1 (continued) parameter symbol absolute maximum value unit notes
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 8 freescale semiconductor electrical characteristics platform supply voltage v dd _plat 1.05 50 mv v ? local bus and platform pll supply voltage av dd _lb, av dd _plat 1.05 50 mv v ? ddr and ddr2 sdram i/o supply voltages d1_gv dd, d2_gv dd 2.5 v 125 mv v 7 1.8 v 90 mv 7 etsec 1 and 2 i/o supply voltage lv dd 3.3 v 165 mv v 8 2.5 v 125 mv v 8 etsec 3 and 4 i/o supply voltage tv dd 3.3 v 165 mv v 8 2.5 v 125 mv v 8 local bus, duart, dma, multiprocessor interrupts, system control & clocking, debug, test, power management, i 2 c, jtag and miscellaneous i/o voltage ov dd 3.3 v 165 mv v 5 input voltage ddr and ddr2 sdram signals d n _ mv in gnd to d n _gv dd v3, 6 ddr and ddr2 sdram reference d n _ mv ref d n _gv dd /2 1% v ? three-speed ethernet signals lv in tv in gnd to lv dd gnd to tv dd v4, 6 duart, local bus, dma, multiprocessor interrupts, system control & clocking, debug, test, power management, i 2 c, jtag and miscellaneous i/o voltage ov in gnd to ov dd v5,6 junction temperature range t j 0 to 105 o c? ?40 to 105 12 notes: 1. core 1 characteristics apply only to mpc8640d 2. if two separate power supplies are used for v dd _core0 and v dd _core1, they must be at the same nominal voltage and the individual power supplies must be tracked and kept within 100 mv of each other during normal run time. 3. caution: d n _ mv in must meet the overshoot/undershoot requirements for d n _gv dd as shown in figure 2 . 4. caution: l/tv in must meet the overshoot/undershoot requirements for l/tv dd as shown in figure 2 during regular run time. 5. caution: ov in must meet the overshoot/undershoot requirements for ov dd as shown in figure 2 during regular run time. 6. timing limitations for m,l,t,o)v in and d n _mv ref during regular run time is provided in figure 2 7. the 2.5 v 125 mv range is for ddr and 1.8 v 90 mv range is for ddr2. 8. see section 8.2, ?fifo, gmii, mii, tbi, rgmii, rmii, and rtbi ac timing specifications ,? for details on the recommended operating conditions per protocol. 9. the pci express interface of the device is expected to receive signals from 0.175 to 1.2 v. for more information refer to section 14.4.3, ?differential receiver (rx) input specifications.? 10. applies to part number mc8640wxx1067nz only. v dd _core n = 0.95 v and v dd _plat = 1.05 v devices. refer to ta ble 7 4 part numbering nomenclature to determine if the device has been marked for v dd _core n = 0.95 v. 11. this voltage is the input to the filter discussed in section 20.2, ?power supply design and sequencing ,? and not necessarily the voltage at the av dd _core n pin, which may be reduced from v dd _core n by the filter. 12. applies to part number mc8640dtxxyyyyaz. refer to ta b l e 7 4 part numbering nomenclature to determine if the device has been marked for extended operating temperature range. table 2. recommended operating conditions (continued) parameter symbol recommended value unit notes
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 freescale semiconductor 9 electrical characteristics figure 2 shows the undershoot and overshoot voltages at the interfaces of the mpc8640. figure 2. overshoot/undershoot voltage for d n _ m/o/l/tv in the mpc8640 core voltage must always be provided at nominal v dd _core n (see table 2 for actual recommended core voltage). voltage to the processor interface i/os are provided through separate sets of supply pins and must be provided at the voltages shown in table 2 . the input voltage threshold scales with respect to the associated i/o supply voltage. ov dd and l/tv dd based receivers are simple cmos i/o circuits and satisfy appropriate lvcmos type specifications. the ddr sdram interface uses a single-ended differential receiver referenced to each externally supplied d n _mv ref signal (nominally set to d n _gv dd /2) as is appropriate for the (sstl-18 and sstl-25) electrical signaling standards. gnd gnd ? 0.3 v gnd ? 0.7 v not to exceed 10% l/t/d n _g/o/x/sv dd + 20% l/t/d n _g/o/x/sv dd l/t/d n _g/o/x/sv dd + 5% of t clk 1 1. t clk references clocks for various functional blocks as follows: v ih v il note: ddrn = 10% of dn_mck period etsecn = 10% of ecn_gtx_clk125 period local bus = 10% of lclk[0:2] period i2c = 10% of sysclk jtag = 10% of sysclk
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 10 freescale semiconductor electrical characteristics 2.1.3 output driver characteristics table 3 provides information on the characteristics of the output driver strengths. the values are preliminary estimates. table 3. output drive capability driver type programmable output impedance ( ) supply voltage notes ddr1 signal 18 36 (half strength mode) d n _gv dd = 2.5 v 4, 9 ddr2 signal 18 36 (half strength mode) d n _gv dd = 1.8 v 1, 5, 9 local bus signals 45 25 ov dd = 3.3 v 2, 6 etsec/10/100 signals 45 t/lv dd = 3.3 v 6 30 t/lv dd = 2.5 v 6 duart, dma, multiprocessor interrupts, system control & clocking, debug, test, power management, jtag and miscellaneous i/o voltage 45 ov dd = 3.3 v 6 i 2 c 150 ov dd = 3.3 v 7 srio, pci express 100 sv dd = 1.1/1.05 v 3, 8 notes: 1. see the ddr control driver registers in the mpc8641d reference manual for more information. 2. only the following local bus signals have programmable drive strengths: lale, lad[0:31], ldp[0:3], la[27:31], lcke, lcs[1:2], lwe[0:3], lgpl1, lgpl2, lgpl3, lgpl4, lgpl5, lclk[0:2]. the other local bus signals have a fixed drive strength of 45 . see the por impedance control register in the mpc8641d reference manual for more information about local bus signals and their drive strength programmability. 3. see section 17, ?signal listings ,? for details on resistor requirements for the calibration of sd n _imp_cal_tx and sd n _imp_cal_rx transmit and receive signals. 4. stub series terminated logic (sstl-25) type pins. 5. stub series terminated logic (sstl-18) type pins. 6. low voltage transistor-transistor logic (lvttl) type pins. 7. open drain type pins. 8. low voltage differential signaling (lvds) type pins. 9. the drive strength of the ddr interface in half strength mode is at t j = 105c and at d n _gv dd (min).
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 freescale semiconductor 11 electrical characteristics 2.2 power-up/down sequence the mpc8640 requires its power rails to be applied in a specific sequence to ensure proper device operation. note the recommended maximum ramp up time for power supplies is 20 milliseconds. the chronological order of power up is: 1. all power rails other than ddr i/o (d n _gv dd , and d n _mv ref ). note there is no required order sequence between the individual rails for this item (# 1). however, v dd _plat, av dd _plat rails must reach 90% of their recommended value before the rail for dn_gv dd , and dn_mv ref (in next step) reaches 10% of their recommended value. av dd type supplies must be delayed with respect to their source supplies by the rc time constant of the pll filter circuit described in section 20.2.1, ?pll power supply filtering . ? 2. d n _gv dd , d n _mv ref note it is possible to leave the related power supply (d n _gv dd , d n _mv ref ) turned off at reset for a ddr port that will not be used. note that these power supplies can only be powered up again at reset for functionality to occur on the ddr port. 3. 3. sysclk the recommended order of power down is as follows: 1. d n _gv dd , d n _mv ref 2. all power rails other than ddr i/o (d n _gv dd , d n _mv ref ). note sysclk may be powered down simultaneous to either of item # 1 or # 2 in the power down sequence. beyond this, the power supplies may power down simultaneously if the preservation of ddr n memory is not a concern. see figure 3 for more details on the power and reset sequencing details.
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 12 freescale semiconductor electrical characteristics figure 3 illustrates the power up sequence as described above. figure 3. mpc8640 power-up and reset sequence v dd _plat, av dd _plat l/t/ov dd time 2.5 v 3.3 v 1.2 v 0 dc power supply voltage reset configuration pins h reset (& trst) 100 s platform pll asserted for 100 s after power supply ramp up 2 notes: 1. dotted waveforms correspond to optional supply values for a specified power supply. see ta b l e 2 . 2. the recommended maximum ramp up time for power supplies is 20 milliseconds. 3. refer to section 5, ?reset initialization ,? for additional information on pll relock and reset signal assertion timing requirements. 4. refer to table 11 for additional information on reset configuration pin setup timing requirements. in addition see figure 68 regarding hreset and jtag connection details including trst . 5. e600 pll relock time is 100 microseconds maximum plus 255 mpx_clk cycles. 6. stable pll configuration signals are required as stable sysclk is applied. all other por configuration inputs are required 4 sysclk cycles before hreset negation and are valid at least 2 sysclk cycles after hreset has negated (hold requirement). see section 5, ?reset initialization ,? for more information on setup and hold time of reset configuration signals. 7. v dd _plat, av dd _plat must strictly reach 90% of their recommended voltage before the rail for d n _gv dd , and d n _mv ref reaches 10% of their recommended voltage. 8. sysclk must be driven only after the power for the various power supplies is stable. 9. in device sleep mode, the reset configuration signals for dram types (tsec2_txd[4],tsec2_tx_er) must be valid before hreset is asserted. e600 5 av dd _lb, sv dd , xv dd _srds n v dd _core n , av dd _core n av dd _srds n 1.8 v d n _gv dd , = 1.8/2.5 v d n _mv ref if sysclk 8 (not drawn to scale) relock time 3 l/tv dd =2.5 v 1 7 pll 9 sysclk is functional 4 cycles setup and hold time 6
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 freescale semiconductor 13 power characteristics 3 power characteristics the power dissipation for the dual core mpc8640d device is shown in table 4 . the power dissipation for individual power supplies of the mpc8640d is shown in table 5 . table 4. mpc8640d power dissipation (dual core) power mode core frequency (mhz) platform frequency (mhz) v dd _coren, v dd _plat (volts) junction temperature power (watts) notes typ i ca l 1250 mhz 500 mhz 1.05 v 65 o c21.71, 2 thermal 105 o c 27.3 1, 3 maximum 31 1, 4 typ i ca l 1000 mhz 500 mhz 1.05 v 65 o c18.91, 2 thermal 105 o c 23.8 1, 3 maximum 27 1, 4 typ i ca l 1067 mhz 533 mhz 0.95/1.05 v 65 o c 15.7 1, 2, 5 thermal 105 o c 19.5 1, 3, 5 maximum 22 1, 4, 5 notes: 1. these values specify the power consumption at nominal voltage and apply to all valid processor bus frequencies and configurations. the values do not include power dissipation for i/o supplies. 2. typical power is an average value measured at the nominal recommended core voltage (v dd _core n ) and 65 c junction temperature (see ta b l e 2 )while running the dhrystone 2.1 benchmark and achieving 2.3 dhrystone mips/mhz with one core at 100% efficiency and the second core at 65% efficiency. 3. thermal power is the average power measured at nominal core voltage (v dd _core n ) and maximum operating junction temperature (see ta b l e 2 ) while running the dhrystone 2.1 benchmark and achieving 2.3 dhrystone mips/mhz on both cores and a typical workload on platform interfaces. 4. maximum power is the maximum power measured at nominal core voltage (v dd _core n ) and maximum operating junction temperature (see ta ble 2 ) while running a test which includes an entirely l1-cache-resident, contrived sequence of instructions which keep all the execution units maximally busy on both cores. 5. these power numbers are for part number mc8640dwxx1067nz and mc8640wxx1067nz only. v dd _core n = 0.95 v and v dd _plat = 1.05 v. table 5. mpc8640d individual supply maximum power dissipation 1 component description supply voltage (volts) power (watts) notes per core voltage supply v dd _core0/v dd _core1 = 1.05 v at 1250 mhz 17.00 ? per core pll voltage supply av dd _core0/av dd _core1 = 1.05 v at 1250 mhz 0.0125 ? per core voltage supply v dd _core0/v dd _core1 = 1.05 v at 1000 mhz 15.00 ? per core pll voltage supply av dd _core0/av dd _core1 = 1.05 v at 1000 mhz 0.0125 ? per core voltage supply v dd _core0/v dd _core1 = 0.95 v at 1067 mhz 11.50 5 per core pll voltage supply av dd _core0/av dd _core1 = 0.95 v at 1067 mhz 0.0125 5 ddr controller i/o voltage supply d n _gv dd = 2.5 v at 400 mhz 0.80 2, 6 d n _gv dd = 1.8 v at 533 mhz 0.68 2, 6
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 14 freescale semiconductor power characteristics the power dissipation for the mpc8640 single core device is shown in table 6 . 16-bit fifo @ 200 mhz etsec 1&2/3&4 voltage supply l/tv dd = 3.3 v 0.11 2, 3, 6 non-fifo etsec n voltage supply l/tv dd = 3.3 v 0.08 2, 6 x8 serdes transceiver supply sv dd = 1.05 v 0.70 2, 6 x8 serdes i/o supply xv dd _srds n = 1.05 v 0.66 2, 6 serdes pll voltage supply port 1 or 2 av dd _srds1/av dd _srds2 = 1.05 v 0.10 2, 6 platform i/o supply ov dd = 3.3 v 0.45 4, 6 platform source supply v dd _plat = 1.05 v at 533 mhz 3.5 ? platform source supply v dd _plat = 1.05 vn at 500 mhz 3.5 5 platform, local bus pll voltage supply av dd _plat, av dd _lb = 1.1 v 0.0125 ? notes: 1. this is a maximum power supply number which is provided for power supply and board design information. the numbers are based on 100% bus utilization for each component. the components listed are not expected to have 100% bus usage simultaneously for all components. actual numbers may vary based on activity. 2. number is based on a per port/interface value. 3. this is based on one etsec port used. since 16-bit fifo mode involves two ports, the number w ill need to be multiplied by two for the total. the other etsec protocols dissipate less than this number per port. note that the power needs to be multiplied by the number of ports used for the protocol for the total etsec port power dissipation. 4.platform i/o includes local bus, duart, i 2 c, dma, multiprocessor interrupts, system control and clocking, debug, test, power management, jtag and miscellaneous i/o voltage. 5. power numbers with v dd _core n = 0.95 v and v dd _plat = 1.05 v are for part number mc8640xxx1067nz only. 6. the maximum power supply number for the i/os are estimates. table 6. mpc8640 power dissipation (single core) power mode core frequency (mhz) platform frequency (mhz) v dd _coren, v dd _plat (volts) junction temperature power (watts) notes ty p i c a l 1250 mhz 500 mhz 1.05 v 65 o c 13.3 1, 2 thermal 105 o c 16.5 1, 3 maximum 19 1, 4 ty p i c a l 1000 mhz 500 mhz 1.05 v 65 o c 11.9 1, 2 thermal 105 o c 14.8 1, 3 maximum 17 1, 4 table 5. mpc8640d individual supply maximum power dissipation (continued) 1 component description supply voltage (volts) power (watts) notes
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 freescale semiconductor 15 input clocks 4 input clocks table provides the system clock (sysclk) dc specifications for the mpc8640. 4.1 system clock timing table 8 provides the system clock (sysclk) ac timing specifications for the mpc8640. ty p i c a l 1067 mhz 533 mhz 0.95 v, 1.05 v 65 o c 10.1 1, 2, 5 thermal 105 o c 12.3 1, 3, 5 maximum 14 1, 4, 5 notes: 1. these values specify the power consumption at nominal voltage and apply to all valid processor bus frequencies and configurations. the values do not include power dissipation for i/o supplies. 2. typical power is an average value measured at the nominal recommended core voltage (v dd _core n ) and 65 c junction temperature (see tab le 2 ) while running the dhrystone 2.1 benchmark and achieving 2.3 dhrystone mips/mhz. 3. thermal power is the average power measured at nominal core voltage (v dd _core n ) and maximum operating junction temperature (see table 2 ) while running the dhrystone 2.1 benchmark and achieving 2.3 dhrystone mips/mhz and a typical workload on platform interfaces. 4. maximum power is the maximum power measured at nominal core voltage (v dd _core n ) and maximum operating junction temperature (see tab le 2 ) while running a test which includes an entirely l1-cache-resident, contrived sequence of instructions which keep all the execution units maximally busy. 5. these power numbers are for part number mc8640dwxx1067nz and mc8640wxx1067nz only. v dd _core n = 0.95 v and v dd _plat = 1.05 v. table 7. sysclk dc electrical characteristics (ov dd = 3.3 v 165 mv) parameter symbol min max unit high-level input voltage v ih 2ov dd + 0.3 v low-level input voltage v il ?0.3 0.8 v input current (v in 1 = 0 v or v in = v dd) i in ?5 a note: 1. note that the symbol v in , in this case, represents the ov in symbol referenced in ta ble 1 and tab le 2 . table 8. sysclk ac timing specifications at recommended operating conditions (see ta b l e 2 ) with ov dd = 3.3 v 165 mv . parameter symbol min typical max unit notes sysclk frequency f sysclk 66 ? 166.66 mhz 1 sysclk cycle time t sysclk 6??ns? sysclk rise and fall time t kh , t kl 0.6 1.0 1.2 ns 2 table 6. mpc8640 power dissipation (single core) (continued) power mode core frequency (mhz) platform frequency (mhz) v dd _coren, v dd _plat (volts) junction temperature power (watts) notes
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 16 freescale semiconductor input clocks 4.1.1 sysclk and spread spectrum sources spread spectrum clock sources are an increasingly popular way to control electromagnetic interference emissions (emi) by spreading the emitted noise to a wider spectrum and reducing the peak noise magnitude in order to meet industr y and government requirements. thes e clock sources intentionally add long-term jitter to diffuse the emi spectral content. the jitter specification given in table 8 considers short-term (cycle-to-cycle) jitter only and the clock ge nerator?s cycle-to-cycle output jitter should meet the mpc8640 input cycle-to-cycle jitter requirement. freque ncy modulation and spread are separate concerns, and the mpc8640 is compatible with spread spectrum sources if the recommendations listed in table 9 are observed. it is imperative to note that the processor?s minimum and maximum sysclk, core, and vco frequencies must not be exceeded regardless of the type of clock source. therefore, systems in which the processor is operated at its maximum rated e 600 core frequency should avoid violating the stated limits by using down-spreading only. sd n _ref_clk and sd n _ref_clk were designed to work with a spread spectrum clock (+0 to 0.5% spreading at 30-33 khz rate is allowed), assuming both ends have same reference clock. for better results, use a source without significant unintended modulation. sysclk duty cycle t khk /t sysclk 40 ? 60 % 3 sysclk jitter ? ? ? 150 ps 4, 5 notes: 1. caution: the mpx clock to sysclk ratio and e600 core to mpx clock ratio settings must be chosen such that the resulting sysclk frequency, e600 (core) frequency, and mpx clock frequency do not exceed their respective maximum or minimum operating frequencies. refer to section 18.2, ?mpx to sysclk pll ratio , ? and section 18.3, ?e600 to mpx clock pll ratio , ? for ratio settings. 2. rise and fall times for sysclk are measured at 0.4 v and 2.7 v. 3. timing is guaranteed by design and characterization. 4. this represents the short term jitter only and is guaranteed by design. 5. the sysclk driver?s closed loop jitter bandwidth should be <500 khz at ?20 db. the bandwidth must be set low to allow cascade-connected pll-based devices to track sysclk drivers with the specified jitter. note that the frequency modulation for sysclk reduces significantly for the spread spectrum source case. this is to guarantee what is supported based on design. table 9. spread spectrum clock source recommendations at recommended operating conditions. see table 2 . parameter min max unit notes frequency modulation ? 50 khz 1 frequency spread ? 1.0 % 1, 2 notes: 1. guaranteed by design. 2. sysclk frequencies resulting from frequency spreading, and the resulting core and vco frequencies, must meet the minimum and maximum specifications given in table 8 . table 8. sysclk ac timing specifications (continued) at recommended operating conditions (see ta b l e 2 ) with ov dd = 3.3 v 165 mv . parameter symbol min typical max unit notes
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 freescale semiconductor 17 input clocks 4.2 real time clock timing the rtc input is sampled by the platform clock (mpx clock). the output of the sampling latch is then used as an input to the counters of the pic. ther e is no jitter specification. the minimum pulse width of the rtc signal should be greater than 2 the period of the mpx clock. that is, minimum clock high time is 2 t mpx , and minimum clock low time is 2 t mpx . there is no minimum rtc frequency; rtc may be grounded if not needed. 4.3 etsec gigabit reference clock timing table 10 provides the etsec gigabit reference clocks (ec1_gtx_clk125 and ec2_gtx_clk125) ac timing specifications for the mpc8640. note the phase between the output clocks tsec1_gtx_clk and tsec2_gtx_clk (ports 1 and 2) is no more than 100 ps. the phase between the output clocks tsec3_gtx_clk and tsec4_gtx_clk (ports 3 and 4) is no more than 100 ps. 4.4 platform frequency requirements for pci-express and serial rapidio the mpx platform clock frequency must be considered for proper operation of the high-speed pci express and serial rapidio interfaces as described below. for proper pci express operation, the mpx clock frequency must be greater than or equal to: 527 mhz x (pci-express link width) 16 / (1 + cfg_plat_freq) table 10 . ec n _gtx_clk125 ac timing specifications parameter symbol min typical max unit notes ec n _gtx_clk125 frequency f g125 ? 125 100 ppm ?mhz3 ec n _gtx_clk125 cycle time t g125 ?8?ns? ec n _gtx_clk125 peak-to-peak jitter t g125j ? ? 250 ps 1 ec n _gtx_clk125 duty cycle gmii, tbi 1000base-t for rgmii, rtbi t g125h /t g125 45 47 ? 55 53 %1, 2 notes: 1. timing is guaranteed by design and characterization. 2. ec n _gtx_clk125 is used to generate the gtx clock for the etsec transmitter with 2% degradation. ec n _gtx_clk125 duty cycle can be loosened from 47/53% as long as the phy device can tolerate the duty cycle generated by the etsec gtx_clk. see section 8.2.6, ?rgmii and rtbi ac timing specifications,? for duty cycle for 10base-t and 100base-t reference clock. 3. 100 ppm tolerance on ec n _gtx_clk125 frequency.
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 18 freescale semiconductor reset initialization note that at mpx = 400 mhz, cfg_plat_freq = 0 and at mpx > 400 mhz, cfg_plat_freq = 1. therefore, when operating pci express in x8 link width, the mpx platform frequency must be 400 mhz with cfg_plat_freq = 0 or greater than or equal to 527 mhz with cfg_plat_freq = 1. for proper serial rapidio operation, the mp x clock frequency must be greater than: 2 (0.80) (serial rapidio interface frequency) (serial rapidio link width) 64 4.5 other input clocks for information on the input clocks of other functional blocks of the platform such as serdes, and etsec, see the specific section of this document. 5 reset initialization this section describes the ac electrical specifications for the reset initialization timing requirements of the mpc8640. table 11 provides the reset initialization ac timing specifications. table 12 provides the pll lock times. table 11. reset initialization timing specifications parameter min max unit notes required assertion time of hreset 100 ? s? minimum assertion time for sreset _0 & sreset _1 3 ? sysclks 1 platform pll input setup time with stable sysclk before hreset negation 100 ? s2 input setup time for por configs (other than pll config) with respect to negation of hreset 4 ? sysclks 1 input hold time for all por configs (including pll config) with respect to negation of hreset 2 ? sysclks 1 maximum valid-to-high impedance time for actively driven por configs with respect to negation of hreset ? 5 sysclks 1 notes: 1. sysclk is the primary clock input for the mpc8640. 2 this is related to hreset assertion time. stable pll configuration inputs are required when a stable sysclk is applied. see the mpc8641d integrated host processor reference manual for more details on the power-on reset sequence. table 12. pll lock times parameter min max unit notes (platform and e600) pll lock times ? 100 s1 local bus pll ? 50 s? notes: 1.the pll lock time for e600 plls require an additional 255 mpx_clk cycles.
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 freescale semiconductor 19 ddr and ddr2 sdram 6 ddr and ddr2 sdram this section describes the dc and ac electrical specifications for the ddr sdram interface of the mpc8640. note that ddr sdram is d n _gv dd (typ) = 2.5 v and ddr2 sdram is d n _gv dd (typ) = 1.8 v. 6.1 ddr sdram dc electrical characteristics table 13 provides the recommended operating conditions for the ddr2 sdram component(s) of the mpc8640 when d n _gv dd (typ) = 1.8 v . table 14 provides the ddr2 capacitance when dn_gv dd(typ) =1.8v. table 13. ddr2 sdram dc electrical characteristics for d n _gv dd (typ) = 1.8 v parameter symbol min max unit notes i/o supply voltage d n _gv dd 1.71 1.89 v 1 i/o reference voltage d n _mv ref 0.49 d n _gv dd 0.51 d n _gv dd v2 i/o termination voltage v tt d n _mv ref ?0.04 d n _mv ref + 0.04 v 3 input high voltage v ih d n _mv ref + 0.125 d n _gv dd +0.3 v ? input low voltage v il ?0.3 d n _mv ref ? 0.125 v ? output leakage current i oz ?50 50 a4 output high current (v out = 1.420 v) i oh ?13.4 ? ma ? output low current (v out = 0.280 v) i ol 13.4 ? ma ? notes: 1. d n _gv dd is expected to be within 50 mv of the dram d n _gv dd at all times. 2. d n _mv ref is expected to be equal to 0.5 d n _gv dd , and to track d n _gv dd dc variations as measured at the receiver. peak-to-peak noise on d n _mv ref may not exceed 2% of the dc value. 3. v tt is not applied directly to the device. it is the supply to which far end signal termination is made and is expected to be equal to d n _mv ref . this rail should track variations in the dc level of d n _mv ref . 4. output leakage is measured with all outputs disabled, 0 v v out d n _gv dd . table 14. ddr2 sdram capacitance for d n _gv dd (typ)=1.8 v parameter symbol min max unit notes input/output capacitance: dq, dqs, dqs c io 68pf1 delta input/output capacitance: dq, dqs, dqs c dio ?0.5pf1 note: 1. this parameter is sampled. d n _gv dd = 1.8 v 0.090 v, f = 1 mhz, t a = 25c, v out = d n _gv dd 2, v out(peak-to-peak) =0.2v.
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 20 freescale semiconductor ddr and ddr2 sdram table 15 provides the recommended operating conditions for the ddr sdram component(s) when d n _gv dd (typ) = 2.5 v . table 16 provides the ddr capacitance when d n _gv dd (typ) = 2.5 v. table 17 provides the current draw characteristics for mv ref . table 15. ddr sdram dc electrical characteristics for d n _gv dd (typ) = 2.5 v parameter symbol min max unit notes i/o supply voltage d n _gv dd 2.375 2.625 v 1 i/o reference voltage d n _mv ref 0.49 d n _gv dd 0.51 d n _gv dd v2 i/o termination voltage v tt d n _mv ref ? 0.04 d n _mv ref + 0.04 v 3 input high voltage v ih d n _mv ref + 0.15 d n _gv dd + 0.3 v ? input low voltage v il ?0.3 d n _mv ref ? 0.15 v ? output leakage current i oz ?50 50 a4 output high current (v out = 1.95 v) i oh ?16.2 ? ma ? output low current (v out = 0.35 v) i ol 16.2 ? ma ? notes: 1. d n _gv dd is expected to be within 50 mv of the dram d n _gv dd at all times. 2. mv ref is expected to be equal to 0.5 d n _gv dd , and to track d n _gv dd dc variations as measured at the receiver. peak-to-peak noise on d n _mv ref may not exceed 2% of the dc value. 3. v tt is not applied directly to the device. it is the supply to which far end signal termination is made and is expected to be equal to d n _mv ref . this rail should track variations in the dc level of d n _mv ref . 4. output leakage is measured with all outputs disabled, 0 v v out d n _gv dd . table 16. ddr sdram capacitance for d n _gv dd (typ) = 2.5 v parameter symbol min max unit notes input/output capacitance: dq, dqs c io 68pf1 delta input/output capacitance: dq, dqs c dio ?0.5pf1 note: 1. this parameter is sampled. d n _gv dd = 2.5 v 0.125 v, f = 1 mhz, t a =25c, v out = d n _gvdd/2, v out (peak-to-peak) = 0.2 v. table 17. current draw characteristics for mv ref parameter symbol min max unit note current draw for mv ref i mvref ?500 a1 1. the voltage regulator for mv ref must be able to supply up to 500 a current.
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 freescale semiconductor 21 ddr and ddr2 sdram 6.2 ddr sdram ac electrical characteristics this section provides the ac electrical characteristics for the ddr sdram interface. 6.2.1 ddr sdram input ac timing specifications table 18 provides the input ac timing specifications for the ddr2 sdram when d n _gv dd(typ) =1.8 v. table 19 provides the input ac timing specifications for the ddr sdram when d n _gv dd(typ) =2.5 v. table 20 provides the input ac timing specifications for the ddr sdram interface. table 18. ddr2 sdram input ac timing specifications for 1.8-v interface at recommended operating conditions (see ta b l e 2 ) parameter symbol min max unit notes ac input low voltage v il ?d n _mv ref ? 0.25 v ? ac input high voltage v ih d n _mv ref + 0.25 ? v ? table 19. ddr sdram input ac timing specifications for 2.5-v interface at recommended operating conditions (see table 2 ) parameter symbol min max unit notes ac input low voltage v il ?d n _mv ref ? 0.31 v ? ac input high voltage v ih d n _mv ref + 0.31 ? v ? table 20. ddr sdram input ac timing specifications at recommended operating conditions (see table 2 ) parameter symbol min max unit notes controller skew for mdqs?mdq/mecc t ciskew ? ? ps 1, 2 533 mhz ? ?300 300 ? 3 400 mhz ? ?365 365 ? ? note: 1. t ciskew represents the total amount of skew consumed by the controller between mdqs[n] and any corresponding bit that will be captured with mdqs[n]. this should be subtracted from the total timing budget. 2. the amount of skew that can be tolerated from mdqs to a corresponding mdq signal is called t diskew .this can be determined by the following equation: t diskew = (t 3 4 ? abs(t ciskew )) where t is the clock period and abs(t ciskew ) is the absolute value of t ciskew . 3. maximum ddr1 frequency is 400 mhz.
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 22 freescale semiconductor ddr and ddr2 sdram figure 4 shows the ddr sdram input timing for the mdqs to mdq skew measurement (tdiskew). figure 4. ddr input timing diagram for tdiskew 6.2.2 ddr sdram output ac timing specifications table 21. ddr sdram output ac timing specifications at recommended operating conditions (see table 2 ). parameter symbol 1 min max unit notes mck[n] cycle time, mck[n]/mck [n] crossing t mck 310ns2 mck duty cycle 533 mhz 400 mhz t mckh /t mck 47 47 53 53 % 8 8 addr/cmd output setup with respect to mck t ddkhas ns 3 533 mhz 1.48 ? 7 400 mhz 1.95 ? addr/cmd output hold with respect to mck t ddkhax ns 3 533 mhz 1.48 ? 7 400 mhz 1.95 ? mcs [n] output setup with respect to mck t ddkhcs ns 3 533 mhz 1.48 ? 7 400 mhz 1.95 ? mcs [n] output hold with respect to mck t ddkhcx ns 3 533 mhz 1.48 ? 7 400 mhz 1.95 ? mck to mdqs skew t ddkhmh ?0.6 0.6 ns 4 mck [n] mck[n] t mck mdq[x] mdqs[n] t diskew d1 d0 t diskew
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 freescale semiconductor 23 ddr and ddr2 sdram note for the addr/cmd setup and hold specifications in table 21 , it is assumed that the clock control register is set to adjust the memory clocks by 1/2 applied cycle. mdq/mecc/mdm output setup with respect to mdqs t ddkhds, t ddklds ps 5 533 mhz 590 ? 7 400 mhz 700 ? mdq/mecc/mdm output hold with respect to mdqs t ddkhdx, t ddkldx ps 5 533 mhz 590 ? 7 400 mhz 700 ? mdqs preamble start t ddkhmp ?0.5 t mck ? 0.6 ?0.5 t mck +0.6 ns 6 mdqs epilogue end t ddkhme ?0.6 0.6 ns 6 note: 1. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. output hold time can be read as ddr timing (dd) from the rising or falling edge of the reference clock (kh or kl) until the output went invalid (ax or dx). for example, t ddkhas symbolizes ddr timing (dd) for the time t mck memory clock reference (k) goes from the high (h) state until outputs (a) are setup (s) or output valid time. also, t ddkldx symbolizes ddr timing (dd) for the time t mck memory clock reference (k) goes low (l) until data outputs (d) are invalid (x) or data output hold time. 2. all mck/mck referenced measurements are made from the crossing of the two signals 0.1 v. 3. addr/cmd includes all ddr sdram output signals except mck/mck , mcs , and mdq/mecc/mdm/mdqs. 4. note that t ddkhmh follows the symbol conventions described in note 1. for example, t ddkhmh describes the ddr timing (dd) from the rising edge of the mck[n] clock (kh) until the mdqs signal is valid (mh). t ddkhmh can be modified through control of the dqs override bits (called wr_data_delay) in the timing_cfg_2 register. this will typically be set to the same delay as the clock adjust in the clk_cntl register. the timing parameters listed in the table assume that these 2 parameters have been set to the same adjustment value. see the mpc8641 integrated processor reference manual for a description and understanding of the timing modifications enabled by use of these bits. 5. determined by maximum possible skew between a data strobe (mdqs) and any corresponding bit of data (mdq), ecc (mecc), or data mask (mdm). the data strobe should be centered inside of the data eye at the pins of the microprocessor. 6. all outputs are referenced to the rising edge of mck[n] at the pins of the microprocessor. note that t ddkhmp follows the symbol conventions described in note 1. 7. maximum ddr1 frequency is 400 mhz 8. per the jedec spec the ddr2 duty cycle at 400 and 533 mhz is the low and high cycle time values. table 21. ddr sdram output ac timing specifications (continued) at recommended operating conditions (see table 2 ). parameter symbol 1 min max unit notes
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 24 freescale semiconductor ddr and ddr2 sdram figure 5 shows the ddr sdram output timing for the mck to mdqs skew measurement (t ddkhmh ). figure 5. timing diagram for tddkhmh figure 6 shows the ddr sdram output timing diagram. figure 6. ddr sdram output timing diagram mdqs mck [n] mck[n] t mck t ddkhmhmax) = 0.6 ns t ddkhmh(min) = ?0.6 ns mdqs addr/cmd t ddkhas ,t ddkhcs t ddkhmh t ddklds t ddkhds mdq[x] mdqs[n] mck [n] mck[n] t mck t ddkldx t ddkhdx d1 d0 t ddkhax ,t ddkhcx write a0 noop t ddkhme t ddkhmp
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 freescale semiconductor 25 duart figure 7 provides the ac test load for the ddr bus. figure 7. ddr ac test load 7duart this section describes the dc and ac electrical specifications fo r the duart interface of the mpc8640. 7.1 duart dc electrical characteristics table 22 provides the dc electrical characteristics for the duart interface. 7.2 duart ac electrical specifications table 23 provides the ac timing parameters for the duart interface. table 22. duart dc electrical characteristics parameter symbol min max unit high-level input voltage v ih 2ov dd + 0.3 v low-level input voltage v il ?0.3 0.8 v input current (v in 1 = 0 v or v in = v dd) i in ?5 a high-level output voltage (ov dd = min, i oh = ?100 a) v oh ov dd ? 0.2 ? v low-level output voltage (ov dd = min, i ol = 100 a) v ol ?0.2 v note: 1. note that the symbol v in , in this case, represents the ov in symbol referenced in ta ble 1 and ta ble 2 . table 23. duart ac timing specifications parameter value unit notes minimum baud rate mpx clock/1,048,576 baud 1,2 maximum baud rate mpx clock/16 baud 1,3 oversample rate 16 ? 1,4 notes: 1. guaranteed by design. 2. mpx clock refers to the platform clock. 3. actual attainable baud rate will be limited by the latency of interrupt processing. 4. the middle of a start bit is detected as the 8 th sampled 0 after the 1-to-0 transition of the start bit. subsequent bit values are sampled each 16 th sample. output z 0 = 50 r l = 50 dn_gv dd /2
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 26 freescale semiconductor ethernet: enhanced three-speed ethernet (etsec), mii management 8 ethernet: enhanced three-speed ethernet (etsec), mii management this section provides the ac and dc electrical characteristics for enhanced three-speed and mii management. 8.1 enhanced three-speed ethernet controller (etsec) (10/100/1gb mbps)?gmii/mii/tbi/rgmii/rtbi/rmii electrical characteristics the electrical characteristics specified here apply to all gigabit media independent interface (gmii), media independent interface (mii), ten-bit interface (tbi), reduced gigabit media independent interface (rgmii), reduced ten-bit interface (rtbi), and reduced media independent interface (rmii) signals except management data i nput/output (mdio) and management data clock (mdc). the rgmii and rtbi interfaces are defined for 2.5 v, while the gmii and tbi interfaces can be operated at 3.3 or 2.5 v. whether the gmii or tbi interface is operated at 3.3 or 2.5 v, the timing is compliant with the ieee 802.3 standard. the rgmii and rtbi interfaces follow the reduced gigabit media-independent interface (rgmii) specification version 1.3 (12/10/2000). the rmii interface follows the rmii consortium rmii specification version 1.2 (3/20/1998). the electrical ch aracteristics for mdio and mdc are specified in section 9, ?ethernet management interface electrical characteristics.? 8.1.1 etsec dc electrical characteristics all gmii, mii, tbi, rgmii, rmii and rtbi drivers and receivers comply with the dc parametric attributes specified in table 24 and table 25 . the potential applied to the input of a gmii, mii, tbi, rgmii, rmii or rtbi receiver may exceed the potential of the receiver?s power supply (that is, a gmii driver powered from a 3.6-v supply driving v oh into a gmii receiver powered from a 2.5-v supply). tolerance for dissimilar gmii driver and receiver suppl y potentials is implicit in these specifications. the rgmii and rtbi signals are based on a 2.5-v cmos interface voltage as defined by jedec eia/jesd8-5. table 24. gmii, mii, rmii, tbi and fifo dc electrical characteristics parameter symbol min max unit notes supply voltage 3.3 v lv dd tv dd 3.135 3.465 v 1, 2 output high voltage (lv dd /tv dd = min, i oh = ?4.0 ma) v oh 2.40 ? v ? output low voltage (lv dd /tv dd = min, i ol = 4.0 ma) v ol ?0.50 v? input high voltage v ih 2.0 ? v ? input low voltage v il ?0.90 v? input high current (v in = lv dd , v in = tv dd ) i ih ?40 a 1, 2, 3
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 freescale semiconductor 27 ethernet: enhanced three-speed ethernet (etsec), mii management 8.2 fifo, gmii, mii, tbi, rgmii, rmii, and rtbi ac timing specifications the ac timing specifications for fifo, gmii, mii, tbi, rgmii, rmii and rtbi are presented in this section. 8.2.1 fifo ac specifications the basis for the ac specifications for the etsec?s fifo modes is the double data rate rgmii and rtbi specifications because they have similar performance and are described in a source-synchronous fashion like fifo modes. however, the fifo interface provide s deliberate skew between the transmitted data and source clock in gmii fashion. when the etsec is configured for fifo modes, all clocks are supplied from external sources to the relevant etsec interface. that is, the transmit clock must be applied to the etsec n ?s tsec n _tx_clk, while the receive clock must be applied to pin tsec n _rx_clk. the etsec internally uses the transmit input low current (v in = gnd) i il ?600 ? a 3 notes: 1. lv dd supports etsecs 1 and 2 2. tv dd supports etsecs 3 and 4 3. the symbol v in , in this case, represents the lv in and tv in symbols referenced in table 1 and ta b l e 2 table 25. gmii, rgmii, rtbi, tbi and fifo dc electrical characteristics parameter symbol min max unit notes supply voltage 2.5 v lv dd /tv dd 2.375 2.625 v 1, 2 1 lv dd supports etsecs 1 and 2. 2 tv dd supports etsecs 3 and 4. output high voltage (lv dd /tv dd = min, i oh = ?1.0 ma) v oh 2.00 ? v ? output low voltage (lv dd /tv dd = min, i ol = 1.0 ma) v ol ?0.40v? input high voltage v ih 1.70 ? v ? input low voltage v il ?0.90v? input high current (v in = lv dd , v in = tv dd ) i ih ?10 a 1, 2, 3 3 note that the symbol v in , in this case, represents the lv in and tv in symbols referenced in ta ble 1 and ta ble 2 . input low current (v in = gnd) i il ?15 ? a 3 note: table 24. gmii, mii, rmii, tbi and fifo dc electrical characteristics (continued) parameter symbol min max unit notes
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 28 freescale semiconductor ethernet: enhanced three-speed ethernet (etsec), mii management clock to synchronously generate tr ansmit data and outputs an echoed copy of the transmit clock back out onto the tsec n _gtx_clk pin (while transmit data appears on tsec n _txd[7:0], for example). it is intended that external receivers capture etsec transmit data using the clock on tsec n _gtx_clk as a source- synchronous timing reference. typically, the cloc k edge that launched the data can be used, since the clock is delayed by the etsec to allow acceptable set-up margin at the receiver. note that there is relationship between the maximum fifo speed and the platform speed. for more information, see section 18.4.2, ?platform to fifo restrictions .? note the phase between the output clocks tsec1_gtx_clk and tsec2_gtx_clk (ports 1 and 2) is no more than 100 ps. the phase between the output clocks tsec3_gtx_clk and tsec4_gtx_clk (ports 3 and 4) is no more than 100 ps. a summary of the fifo ac specifications appears in table 26 and table 27 . table 26. fifo mode transmit ac timing specification at recommended operating conditions with l/tv dd of 3.3 v 5% and 2.5 v 5%. parameter symbol min typ max unit tx_clk, gtx_clk clock period (gmii mode) t fit 8.4 8.0 100 ns tx_clk, gtx_clk clock period (encoded mode) t fit 6.4 8.0 100 ns tx_clk, gtx_clk duty cycle t fith/ t fit 45 50 55 % tx_clk, gtx_clk peak-to-peak jitter t fitj ? ? 250 ps rise time tx_clk (20%?80%) t fitr ? ? 0.75 ns fall time tx_clk (80%?20%) t fitf ? ? 0.75 ns fifo data txd[7:0], tx_er, tx_en setup time to gtx_clk t fitdv 2.0 ? ? ns gtx_clk to fifo data txd[7:0], tx_er, tx_en hold time t fitdx 0.5 ? 3.0 ns table 27. fifo mode receive ac timing specification at recommended operating conditions with l/tv dd of 3.3 v 5% and 2.5 v 5%. parameter symbol min typ max unit rx_clk clock period (gmii mode) t fir 1 8.4 8.0 100 ns rx_clk clock period (encoded mode) t fir 1 6.4 8.0 100 ns rx_clk duty cycle t firh /t fir 45 50 55 % rx_clk peak-to-peak jitter t firj ? ? 250 ps rise time rx_clk (20%?80%) t firr ? ? 0.75 ns fall time rx_clk (80%?20%) t firf ? ? 0.75 ns rxd[7:0], rx_dv, rx_er setup time to rx_clk t firdv 1.5 ? ? ns rxd[7:0], rx_dv, rx_er hold time to rx_clk t firdx 0.5 ? ? ns
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 freescale semiconductor 29 ethernet: enhanced three-speed ethernet (etsec), mii management timing diagrams for fifo appear in figure 8 and figure 9 . . figure 8. fifo transmit ac timing diagram figure 9. fifo receive ac timing diagram 8.2.2 gmii ac timing specifications this section describes the gmii transmit and receive ac timing specifications. 8.2.2.1 gmii transmit ac timing specifications table 28 provides the gmii transmit ac timing specifications. 1 100 ppm tolerance on rx_clk frequency table 28. gmii transmit ac timing specifications at recommended operating conditions with l/tv dd of 3.3 v 5% and 2.5 v 5%. parameter symbol 1 min typ max unit gmii data txd[7:0], tx_er, tx_en setup time t gtkhdv 2.5 ? ? ns gtx_clk to gmii data txd[7:0], tx_er, tx_en delay t gtkhdx 0.5 ? 5.0 ns gtx_clk data clock rise time (20%?80%) t gtxr 2 ??1.0ns t fit t fith t fitf t fitdx txd[7:0] tx_en gtx_clk tx_er t fitdv t fitr t fir t firh t firf t firr rx_clk rxd[7:0] rx_dv rx_er valid data t firdx t firdv
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 30 freescale semiconductor ethernet: enhanced three-speed ethernet (etsec), mii management figure 10 shows the gmii transmit ac timing diagram. figure 10. gmii transmit ac timing diagram 8.2.2.2 gmii receive ac timing specifications table 29 provides the gmii receive ac timing specifications. gtx_clk data clock fall time (80%?20%) t gtxf 2 ??1.0ns notes: 1. the symbols used for timing specifications herein follow the pattern t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t gtkhdv symbolizes gmii transmit timing (gt) with respect to the t gtx clock reference (k) going to the high state (h) relative to the time date input signals (d) reaching the valid state (v) to state or setup time. also, t gtkhdx symbolizes gmii transmit timing (gt) with respect to the t gtx clock reference (k) going to the high state (h) relative to the time date input signals (d) going invalid (x) or hold time. note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. for example, the subscript of t gtx represents the gmii(g) transmit (tx) clock. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). 2. guaranteed by design. table 29. gmii receive ac timing specifications at recommended operating conditions with l/tv dd of 3.3 v 5% and 2.5 v 5%. parameter symbol 1 min typ max unit rx_clk clock period t grx 3 ?8.0? ns rx_clk duty cycle t grxh /t grx 40 ? 60 ns rxd[7:0], rx_dv, rx_er setup time to rx_clk t grdvkh 2.0 ? ? ns rxd[7:0], rx_dv, rx_er hold time to rx_clk t grdxkh 0.5 ? ? ns rx_clk clock rise time (20%?80%) t grxr 2 ??1.0ns table 28. gmii transmit ac timing specifications (continued) at recommended operating conditions with l/tv dd of 3.3 v 5% and 2.5 v 5%. parameter symbol 1 min typ max unit gtx_clk txd[7:0] t gtkhdx t gtx t gtxh t gtxr t gtxf t gtkhdv tx_en tx_er
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 freescale semiconductor 31 ethernet: enhanced three-speed ethernet (etsec), mii management figure 11 provides the ac test load for etsec. figure 11. etsec ac test load figure 12 shows the gmii receive ac timing diagram. figure 12. gmii receive ac timing diagram 8.2.3 mii ac timing specifications this section describes the mii transmit and receive ac timing specifications. rx_clk clock fall time (80%-20%) t grxf 2 ??1.0ns note: 1. the symbols used for timing specifications herein follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t grdvkh symbolizes gmii receive timing (gr) with respect to the time data input signals (d) reaching the valid state (v) relative to the t rx clock reference (k) going to the high state (h) or setup time. also, t grdxkl symbolizes gmii receive timing (gr) with respect to the time data input signals (d) went invalid (x) relative to the t grx clock reference (k) going to the low (l) state or hold time. note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particul ar functional. for example, the subscript of t grx represents the gmii (g) receive (rx) clock. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). 2. guaranteed by design. 3. 100 ppm tolerance on rx_clk frequency table 29. gmii receive ac timing specifications (continued) at recommended operating conditions with l/tv dd of 3.3 v 5% and 2.5 v 5%. parameter symbol 1 min typ max unit output lv dd /2 r l = 50 z 0 = 50 rx_clk rxd[7:0] t grdxkh t grx t grxh t grxr t grxf t grdvkh rx_dv rx_er
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 32 freescale semiconductor ethernet: enhanced three-speed ethernet (etsec), mii management 8.2.3.1 mii transmit ac timing specifications table 30 provides the mii transmit ac timing specifications. figure 13 shows the mii transmit ac timing diagram. figure 13. mii transmit ac timing diagram 8.2.3.2 mii receive ac timing specifications table 31 provides the mii receive ac timing specifications. table 30. mii transmit ac timing specifications at recommended operating conditions with l/tv dd of 3.3 v 5%. parameter symbol 1 min typ max unit tx_clk clock period 10 mbps t mtx 2 ? 400 ? ns tx_clk clock period 100 mbps t mtx ?40?ns tx_clk duty cycle t mtxh/ t mtx 35 ? 65 % tx_clk to mii data txd[3:0], tx_er, tx_en delay t mtkhdx 1 5 15 ns tx_clk data clock rise time (20%?80%) t mtxr 2 1.0 ? 4.0 ns tx_clk data clock fall time (80%?20%) t mtxf 2 1.0 ? 4.0 ns note: 1. the symbols used for timing specifications herein follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t mtkhdx symbolizes mii transmit timing (mt) for the time t mtx clock reference (k) going high (h) until data outputs (d) are invalid (x). note that, in general, the clock reference symbol representation is based on two to three letters representing the clock of a particular functional. for example, the subscript of t mtx represents the mii(m) transmit (tx) clock. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). 2. guaranteed by design. table 31. mii receive ac timing specifications at recommended operating conditions with l/tv dd of 3.3 v 5%. parameter symbol 1 min typ max unit rx_clk clock period 10 mbps t mrx 2,3 ?400? ns rx_clk clock period 100 mbps t mrx 3 ?40?ns rx_clk duty cycle t mrxh /t mrx 35 ? 65 % tx_clk txd[3:0] t mtkhdx t mtx t mtxh t mtxr t mtxf tx_en tx_er
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 freescale semiconductor 33 ethernet: enhanced three-speed ethernet (etsec), mii management figure 14 provides the ac test load for etsec. figure 14. etsec ac test load figure 15 shows the mii receive ac timing diagram. figure 15. mii receive ac timing diagram 8.2.4 tbi ac timing specifications this section describes the tbi trans mit and receive ac timing specifications. rxd[3:0], rx_dv, rx_er setup time to rx_clk t mrdvkh 10.0 ? ? ns rxd[3:0], rx_dv, rx_er hold time to rx_clk t mrdxkh 10.0 ? ? ns rx_clk clock rise time (20%?80%) t mrxr 2 1.0?4.0ns rx_clk clock fall time (80%?20%) t mrxf 2 1.0?4.0ns note: 1. the symbols used for timing specifications herein follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t mrdvkh symbolizes mii receive timing (mr) with respect to the time data input signals (d) reach the valid state (v) relative to the t mrx clock reference (k) going to the high (h) state or setup time. also, t mrdxkl symbolizes mii receive timing (gr) with respect to the time data input signals (d) went invalid (x) relative to the t mrx clock reference (k) going to the low (l) state or hold time. note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. for example, the subscript of t mrx represents the mii (m) receive (rx) clock. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). 2. guaranteed by design. 3. 100 ppm tolerance on rx_clk frequency table 31. mii receive ac timing specifications (continued) at recommended operating conditions with l/tv dd of 3.3 v 5%. parameter symbol 1 min typ max unit output z 0 = 50 lv dd /2 r l = 50 rx_clk rxd[3:0] t mrdxkl t mrx t mrxh t mrxr t mrxf rx_dv rx_er t mrdvkh valid data
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 34 freescale semiconductor ethernet: enhanced three-speed ethernet (etsec), mii management 8.2.4.1 tbi transmit ac timing specifications table 32 provides the tbi transmit ac timing specifications. table 32. tbi transmit ac timing specifications at recommended operating conditions with l/tv dd of 3.3 v 5% and 2.5 v 5%. parameter symbol 1 min typ max unit tcg[9:0] setup time gtx_clk going high t ttkhdv 2.0 ? ? ns tcg[9:0] hold time from gtx_clk going high t ttkhdx 1.0 ? ? ns gtx_clk rise time (20%?80%) t ttxr 2 ??1.0ns gtx_clk fall time (80%?20%) t ttxf 2 ??1.0ns notes: 1. the symbols used for timing specifications herein follow the pattern of t (first two letters of functional block)(signal)(state )(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t ttkhdv symbolizes the tbi transmit timing (tt) with respect to the time from t ttx (k) going high (h) until the referenced data signals (d) reach the valid state (v) or setup time. also, t ttkhdx symbolizes the tbi transmit timing (tt) with respect to the time from t ttx (k) going high (h) until the referenced data signals (d) reach the invalid state (x) or hold time. note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. for example, the subscript of t ttx represents the tbi (t) transmit (tx) clock. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). 2. guaranteed by design.
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 freescale semiconductor 35 ethernet: enhanced three-speed ethernet (etsec), mii management figure 16 shows the tbi transmit ac timing diagram. figure 16. tbi transmit ac timing diagram 8.2.4.2 tbi receive ac timing specifications table 33 provides the tbi receive ac timing specifications. table 33. tbi receive ac timing specifications at recommended operating conditions with l/tv dd of 3.3 v 5% and 2.5 v 5%. parameter symbol 1 min typ max unit pma_rx_clk[0:1] clock period t trx 3 ? 16.0 ? ns pma_rx_clk[0:1] skew t sktrx 7.5?8.5ns pma_rx_clk[0:1] duty cycle t trxh /t trx 40 ? 60 % rcg[9:0] setup time to rising pma_rx_clk t trdvkh 2.5 ? ? ns rcg[9:0] hold time to rising pma_rx_clk t trdxkh 1.5 ? ? ns pma_rx_clk[0:1] clock rise time (20%?80%) t trxr 2 0.7?2.4ns pma_rx_clk[0:1] clock fall time (80%?20%) t trxf 2 0.7?2.4ns note: 1. the symbols used for timing specifications herein follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t trdvkh symbolizes tbi receive timing (tr) with respect to the time data input signals (d) reach the valid state (v) relative to the t trx clock reference (k) going to the high (h) state or setup time. also, t trdxkh symbolizes tbi receive timing (tr) with respect to the time data input signals (d) went invalid (x) relative to the t trx clock reference (k) going to the high (h) state. note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. for example, the subscript of t trx represents the tbi (t) receive (rx) clock. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). for symbols representing skews, the subscript is skew (sk) followed by the clock that is being skewed (trx). 2. guaranteed by design. 3. 100 ppm tolerance on pma_rx_clk[0:1] frequency gtx_clk tcg[9:0] t ttxr t ttx t ttxh t ttxr t ttxf t ttkhdv t ttkhdx t ttxf
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 36 freescale semiconductor ethernet: enhanced three-speed ethernet (etsec), mii management figure 17 shows the tbi receive ac timing diagram. figure 17. tbi receive ac timing diagram 8.2.5 tbi single-clock mode ac specifications when the etsec is configured for tbi modes, all cloc ks are supplied from external sources to the relevant etsec interface. in single-clock tbi mode, when tbicon[clksel] = 1 a 125-mhz tbi receive clock is supplied on tsec n _rx_clk pin (no receive clock is used on tsec n _tx_clk in this mode, whereas for the dual-clock mode this is the pma1 receive clock). the 125-mhz transmit clock is applied on the tsec_gtx_clk125 pin in all tbi modes. a summary of the single-clock tbi mode ac specifications for receive appears in table 34 . table 34. tbi single-clock mode receive ac timing specification at recommended operating conditions with l/tv dd of 3.3 v 5% and 2.5 v 5%. parameter symbol min typ max unit rx_clk clock period t trr 1 1 100 ppm tolerance on rx_clk frequency 7.5 8.0 8.5 ns rx_clk duty cycle t trrh/ t trr 40 50 60 % rx_clk peak-to-peak jitter t trrj ? ? 250 ps rise time rx_clk (20%?80%) t trrr ??1.0ns fall time rx_clk (80%?20%) t trrf ??1.0ns rcg[9:0] setup time to rx_clk rising edge t trrdvkh 2.0 ? ? ns rcg[9:0] hold time to rx_clk rising edge t trrdxkh 1.0 ? ? ns pma_rx_clk1 rcg[9:0] t trx t trxh t trxr t trxf t trdvkh pma_rx_clk0 t trdxkh t trdvkh t trdxkh t sktrx t trxh valid data valid data
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 freescale semiconductor 37 ethernet: enhanced three-speed ethernet (etsec), mii management a timing diagram for tbi receive appears in figure 18 . figure 18. tbi single-clock mode receive ac timing diagram 8.2.6 rgmii and rtbi ac timing specifications table 35 presents the rgmii and rtbi ac timing specifications. table 35. rgmii and rtbi ac timing specifications at recommended operating conditions with l/tv dd of 2.5 v 5%. parameter symbol 1 min typ max unit data to clock output skew (at transmitter) t skrgt 5 ?500 0 500 ps data to clock input skew (at receiver) 2 t skrgt 1.0 ? 2.8 ns clock period duration 3 t rgt 5,6 7.2 8.0 8.8 ns duty cycle for 10base-t and 100base-tx 3, 4 t rgth /t rgt 5 40 50 60 % rise time (20%?80%) t rgtr 5 ? ? 0.75 ns fall time (80%?20%) t rgtf 5 ? ? 0.75 ns notes: 1. note that, in general, the clock reference symbol representation for this section is based on the symbols rgt to represent rgmii and rtbi timing. for example, the subscript of t rgt represents the tbi (t) receive (rx) clock. note also that the notation for rise (r) and fall (f) times follows the clock symbol that is being represented. for symbols representing skews, the subscript is skew (sk) followed by the clock that is being skewed (rgt). 2. this implies that pc board design will require clocks to be routed such that an additional trace delay of greater than 1.5 ns will be added to the associated clock signal. 3. for 10 and 100 mbps, t rgt scales to 400 ns 40 ns and 40 ns 4 ns, respectively. 4. duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains as long as the minimum duty cycle is not violated and stretching occurs for no more than three t rgt of the lowest speed transitioned between. 5. guaranteed by characterization 6. 100 ppm tolerance on rx_clk frequency. t trr t trrh t trrf t trrr rx_clk rcg[9:0] valid data t trrdxkh t trrdvkh
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 38 freescale semiconductor ethernet: enhanced three-speed ethernet (etsec), mii management figure 19 shows the rgmii and rtbi ac timing and multiplexing diagrams. figure 19. rgmii and rtbi ac timing and multiplexing diagrams 8.2.7 rmii ac timing specifications this section describes the rmii transmit and receive ac timing specifications. 8.2.7.1 rmii transmit ac timing specifications the rmii transmit ac timing specifications are in table 36 . table 36. rmii transmit ac timing specifications at recommended operating conditions with l/tv dd of 3.3 v 5%. parameter symbol 1 min typ max unit ref_clk clock period t rmt ? 20.0 ? ns ref_clk duty cycle t rmth /t rmt 35 50 65 % ref_clk peak-to-peak jitter t rmtj ? ? 250 ps rise time ref_clk (20%?80%) t rmtr 1.0 ? 2.0 ns fall time ref_clk (80%?20%) t rmtf 1.0 ? 2.0 ns gtx_clk t rgt t rgth t skrgt tx_ctl txd[8:5] txd[7:4] txd[9] txerr txd[4] txen txd[3:0] (at transmitter) txd[8:5][3:0] txd[7:4][3:0] tx_clk (at phy) rx_ctl rxd[8:5] rxd[7:4] rxd[9] rxerr rxd[4] rxdv rxd[3:0] rxd[8:5][3:0] rxd[7:4][3:0] rx_clk (at phy) t skrgt t skrgt t skrgt
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 freescale semiconductor 39 ethernet: enhanced three-speed ethernet (etsec), mii management figure 20 shows the rmii transmit ac timing diagram. figure 20. rmii transmit ac timing diagram 8.2.7.2 rmii receive ac timing specifications table 37 shows the rmii receive ac timing specifications. ref_clk to rmii data txd[1:0], tx_en delay t rmtdx 1.0 ? 10.0 ns note: 1. the symbols used for timing specifications herein follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t mtkhdx symbolizes mii transmit timing (mt) for the time t mtx clock reference (k) going high (h) until data outputs (d) are invalid (x). note that, in general, the clock reference symbol representation is based on two to three letters representing the clock of a particular functional. for example, the subscript of t mtx represents the mii(m) transmit (tx) clock. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). table 37. rmii receive ac timing specifications at recommended operating conditions with l/tv dd of 3.3 v 5%. parameter symbol 1 min typ max unit ref_clk clock period t rmr 15.0 20.0 25.0 ns ref_clk duty cycle t rmrh /t rmr 35 50 65 % ref_clk peak-to-peak jitter t rmrj ? ? 250 ps rise time ref_clk (20%?80%) t rmrr 1.0 ? 2.0 ns fall time ref_clk (80%?20%) t rmrf 1.0 ? 2.0 ns rxd[1:0], crs_dv, rx_er setup time to ref_clk rising edge t rmrdv 4.0 ? ? ns table 36. rmii transmit ac timing specifications (continued) at recommended operating conditions with l/tv dd of 3.3 v 5%. parameter symbol 1 min typ max unit ref_clk txd[1:0] t rmtdx t rmt t rmth t rmtr t rmtf tx_en tx_er
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 40 freescale semiconductor ethernet management interface electrical characteristics figure 21 provides the ac test load for etsec. figure 21. etsec ac test load figure 22 shows the rmii receive ac timing diagram. figure 22. rmii receive ac timing diagram 9 ethernet management interface electrical characteristics the electrical characteristics specified here apply to mii management interface signals mdio (management data input/output) and mdc (management data clock). the electrical characteristics for gmii, rgmii, rmii, tbi and rtbi are specified in ? section 8, ?ethernet: enhanced three-speed ethernet (etsec), mii management.? rxd[1:0], crs_dv, rx_er hold time to ref_clk rising edge t rmrdx 2.0 ? ? ns note: 1. the symbols used for timing specifications herein follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t mrdvkh symbolizes mii receive timing (mr) with respect to the time data input signals (d) reach the valid state (v) relative to the t mrx clock reference (k) going to the high (h) state or setup time. also, t mrdxkl symbolizes mii receive timing (gr) with respect to the time data input signals (d) went invalid (x) relative to the t mrx clock reference (k) going to the low (l) state or hold time. note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. for example, the subscript of t mrx represents the mii (m) receive (rx) clock. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). table 37. rmii receive ac timing specifications (continued) at recommended operating conditions with l/tv dd of 3.3 v 5%. parameter symbol 1 min typ max unit output z 0 = 50 lv dd /2 r l = 50 ref_clk rxd[1:0] t rmrdx t rmr t rmrh t rmrr t rmrf crs_dv rx_er t rmrdv valid data
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 freescale semiconductor 41 ethernet management interface electrical characteristics 9.1 mii management dc electrical characteristics the mdc and mdio are defined to operate at a supply vo ltage of 3.3 v. the dc electrical characteristics for mdio and mdc are provided in table 38 . 9.2 mii management ac electrical specifications table 39 provides the mii management ac timing specifications. table 38. mii management dc electrical characteristics parameter symbol min max unit supply voltage (3.3 v) ov dd 3.135 3.465 v output high voltage (ov dd = min, i oh = ?1.0 ma) v oh 2.10 ? v output low voltage (ov dd = min, i ol = 1.0 ma) v ol ?0.50v input high voltage v ih 1.70 ? v input low voltage v il ?0.90v input high current (ov dd = max, v in 1 = 2.1 v) i ih ?40 a input low current (ov dd = max, v in = 0.5 v) i il ?600 ? a note: 1. note that the symbol v in , in this case, represents the ov in symbol referenced in ta ble 1 and ta ble 2 . table 39. mii management ac timing specifications at recommended operating conditions with ov dd is 3.3 v 5%. parameter symbol 1 min typ max unit notes mdc frequency f mdc 2.5 ? 9.3 mhz 2, 4 mdc period t mdc 80 ? 400 ns ? mdc clock pulse width high t mdch 32 ? ? ns ? mdc to mdio valid t mdkhdv 16 t mpxclk ??ns5 mdc to mdio delay t mdkhdx 10 ? 16 t mpxclk ns 3, 5 mdio to mdc setup time t mddvkh 5??ns? mdio to mdc hold time t mddxkh 0??ns? mdc rise time t mdcr ? ? 10 ns 4
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 42 freescale semiconductor ethernet management interface electrical characteristics figure 23 provides the ac test load for etsec. figure 23. etsec ac test load note output will see a 50 load since what it sees is the transmission line. figure 24 shows the mii management ac timing diagram. figure 24. mii management interface timing diagram mdc fall time t mdhf ? ? 10 ns 4 notes: 1. the symbols used for timing specifications herein follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t mdkhdx symbolizes management data timing (md) for the time t mdc from clock reference (k) high (h) until data outputs (d) are invalid (x) or data hold time. also, t mddvkh symbolizes management data timing (md) with respect to the time data input signals (d) reach the valid state (v) relative to the t mdc clock reference (k) going to the high (h) state or setup time. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). 2. this parameter is dependent on the system clock speed. (the maximum frequency is the maximum platform frequency divided by 64.) 3. this parameter is dependent on the system clock speed. (that is, for a system clock of 267 mhz, the maximum frequency is 8.3 mhz and the minimum frequency is 1.2 mhz; for a system clock of 375 mhz, the maximum frequency is 11.7 mhz and the minimum frequency is 1.7 mhz.) 4. guaranteed by design. 5. t mpxclk is the platform (mpx) clock table 39. mii management ac timing specifications (continued) at recommended operating conditions with ov dd is 3.3 v 5%. parameter symbol 1 min typ max unit notes output z 0 = 50 ov dd /2 r l = 50 mdc t mddxkh t mdc t mdch t mdcr t mdcf t mddvkh t mdkhdx mdio mdio (input) (output)
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 freescale semiconductor 43 local bus 10 local bus this section describes the dc and ac electrical speci fications for the local bus interface of the mpc8640. 10.1 local bus dc electrical characteristics table 40 provides the dc electrical characteristics for the local bus interface operating at ov dd = 3.3 v dc. 10.2 local bus ac timing specifications table 41 describes the timing parameters of the local bus interface at ov dd = 3.3 v with pll enabled. for information about the frequency range of local bus see section 18.1, ?clock ranges.? table 40. local bus dc electrical characteristics (3.3 v dc) parameter symbol min max unit high-level input voltage v ih 2ov dd + 0.3 v low-level input voltage v il ?0.3 0.8 v input current (v in 1 = 0 v or v in = ov dd ) i in ?5 a high-level output voltage (ov dd = min, i oh = ?2 ma) v oh ov dd ? 0.2 ? v low-level output voltage (ov dd = min, i ol = 2 ma) v ol ?0.2 v note: 1. note that the symbol v in , in this case, represents the ov in symbol referenced in tab le 1 and table 2 . table 41. local bus timing specifications (ov dd = 3.3 v)?pll enabled parameter symbol 1 min max unit notes local bus cycle time t lbk 8?ns2 local bus duty cycle t lbkh /t lbk 45 55 % ? lclk[n] skew to lclk[m] or lsync_out t lbkskew ? 150 ps 7, 8 input setup to local bus clock (except lgta /lupwait) t lbivkh1 1.8 ? ns 3, 4 lgta /lupwait input setup to local bus clock t lbivkh2 1.7 ? ns 3, 4 input hold from local bus clock (except lgta /lupwait) t lbixkh1 1.0 ? ns 3, 4 lgta /lupwait input hold from local bus clock t lbixkh2 1.0 ? ns 3, 4 lale output transition to lad/ldp output transition (latch hold time) t lbotot 1.5 ? ns 6 local bus clock to output valid (except lad/ldp and lale) t lbkhov1 ?2.0ns ? local bus clock to data valid for lad/ldp t lbkhov2 ?2.2ns ? local bus clock to address valid for lad t lbkhov3 ?2.3ns ? local bus clock to lale assertion t lbkhov4 ?2.3ns 3
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 44 freescale semiconductor local bus figure 25 provides the ac test load for the local bus. figure 25. local bus ac test load output hold from local bus clock (except lad/ldp and lale) t lbkhox1 0.7 ? ns ? output hold from local bus clock for lad/ldp t lbkhox2 0.7 ? ns 3 local bus clock to output high impedance (except lad/ldp and lale) t lbkhoz1 ?2.5ns 5 local bus clock to output high impedance for lad/ldp t lbkhoz2 ?2.5ns 5 note: 1. the symbols used for timing specifications herein follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t lbixkh1 symbolizes local bus timing (lb) for the input (i) to go invalid (x) with respect to the time the t lbk clock reference (k) goes high (h), in this case for clock one(1). also, t lbkhox symbolizes local bus timing (lb) for the t lbk clock reference (k) to go high (h), with respect to the output (o) going invalid (x) or output hold time. 2. all timings are in reference to lsync_in for pll enabled and internal local bus clock for pll bypass mode. 3. all signals are measured from ov dd 2 of the rising edge of lsync_in for pll enabled or internal local bus clock for pll bypass mode to 0.4 ov dd of the signal in question for 3.3-v signaling levels. 4. input timings are measured at the pin. 5. for purposes of active/float timing measurements, the hi-z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 6. t lbotot is a measurement of the minimum time between the negation of lale and any change in lad. t lbotot is programmed with the lbcr[ahd] parameter. 7. maximum possible clock skew between a clock lclk[m] and a relative clock lclk[ n ]. skew measured between complementary signals at bv dd 2. 8. guaranteed by design. table 41. local bus timing specifications (ov dd = 3.3 v)?pll enabled (continued) parameter symbol 1 min max unit notes output z 0 = 50 ov dd /2 r l = 50
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 freescale semiconductor 45 local bus figure 26 shows the local bus signals with pll enabled. figure 26. local bus signals (pll enabled) note pll bypass mode is recommended when lbiu frequency is at or below 83 mhz. when lbiu operates above 83 mhz, lbiu pll is recommended to be enabled. table 42 describes the general timing parameters of the local bus interface at ov dd = 3.3 v with pll bypassed. table 42. local bus timing parameters?pll bypassed parameter symbol 1 min max unit notes local bus cycle time t lbk 12 ? ns 2 local bus duty cycle t lbkh/ t lbk 45 55 % ? internal launch/capture clock to lclk delay t lbkhkt 2.3 3.9 ns 8 input setup to local bus clock (except lgta /lupwait) t lbivkh1 5.7 ? ns 4, 5 lgta /lupwait input setup to local bus clock t lbivkl2 5.6 ? ns 4, 5 input hold from local bus clock (except lgta /lupwait) t lbixkh1 ?1.8 ? ns 4, 5 output signals: la[27:31]/lbctl/lbcke/loe / lsda10/lsdwe/lsdras / lsdcas /lsddqm[0:3] t lbkhov1 t lbkhov2 t lbkhov3 lsync_in input signals: lad[0:31]/ldp[0:3] output (data) signals: lad[0:31]/ldp[0:3] output (address) signal: lad[0:31] lale t lbixkh1 t lbivkh1 t lbivkh2 t lbixkh2 t lbkhox1 t lbkhoz1 t lbkhox2 t lbkhoz2 input signal: lgta t lbotot t lbkhoz2 t lbkhox2 t lbkhov4 lupwait
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 46 freescale semiconductor local bus lgta /lupwait input hold from local bus clock t lbixkl2 ?1.3 ? ns 4, 5 lale output transition to lad/ldp output transition (latch hold time) t lbotot 1.5 ? ns 6 local bus clock to output valid (except lad/ldp and lale) t lbklov1 ? ?0.3 ns local bus clock to data valid for lad/ldp t lbklov2 ? ?0.1 ns 4 local bus clock to address valid for lad t lbklov3 ?0ns4 local bus clock to lale assertion t lbklov4 ?0ns4 output hold from local bus clock (except lad/ldp and lale) t lbklox1 ?3.2 ? ns 4 output hold from local bus clock for lad/ldp t lbklox2 ?3.2 ? ns 4 local bus clock to output high impedance (except lad/ldp and lale) t lbkloz1 ?0.2ns7 local bus clock to output high impedance for lad/ldp t lbkloz2 ?0.2ns7 notes: 1. the symbols used for timing specifications herein follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t lbixkh1 symbolizes local bus timing (lb) for the input (i) to go invalid (x) with respect to the time the t lbk clock reference (k) goes high (h), in this case for clock one(1). also, t lbkhox symbolizes local bus timing (lb) for the t lbk clock reference (k) to go high (h), with respect to the output (o) going invalid (x) or output hold time. 2. all timings are in reference to local bus clock for pll bypass mode. timings may be negative with respect to the local bus clock because the actual launch and capture of signals is done with the internal launch/capture clock, which precedes lclk by t lbkhkt . 3. maximum possible clock skew between a clock lclk[m] and a relative clock lclk[n]. skew measured between complementary signals at bv dd 2. 4. all signals are measured from bv dd 2 of the rising edge of local bus clock for pll bypass mode to 0.4 bv dd of the signal in question for 3.3-v signaling levels. 5. input timings are measured at the pin. 6. the value of t lbotot is the measurement of the minimum time between the negation of lale and any change in lad 7. for purposes of active/float timing measurements, the hi-z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 8. guaranteed by characterization. table 42. local bus timing parameters?pll bypassed (continued) parameter symbol 1 min max unit notes
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 freescale semiconductor 47 local bus figure 27 shows the local bus signals in pll bypass mode. figure 27. local bus signals (pll bypass mode) note in pll bypass mode, lclk[ n ] is the inverted version of the internal clock with the delay of t lbkhkt. in this mode, signals are launched at the rising edge of the internal clock and are captured at falling edge of the internal clock, with the exception of the lgta /lupwait signal, which is captured at the rising edge of the internal clock. output signals: la[27:31]/lbctl/lbcke/loe / lsda10/lsdwe/lsdras / lsdcas /lsddqm[0:3] t lbklov2 lclk[n] input signals: lad[0:31]/ldp[0:3] output (data) signals: lad[0:31]/ldp[0:3] lale t lbixkh1 input signal: lgta output (address) signal: lad[0:31] t lbivkh1 t lbixkl2 t lbivkl2 t lbklox1 t lbkloz2 t lbotot internal launch/capture clock t lbklox2 t lbklov1 t lbklov3 t lbkloz1 t lbkhkt t lbklov4 lupwait
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 48 freescale semiconductor local bus figure 28 ? figure 31 show the local bus signals and gpcm/upm signals for lcrr[clkdiv ] at clock ratios of 4, 8, and 16 with pll enabled or bypassed. figure 28. local bus signals, gpcm/upm signals for lcrr[clkdiv] = 2 (clock ratio of 4) (pll enabled) lsync_in upm mode input signal: lupwait t lbixkh2 t lbivkh2 t lbivkh1 t lbixkh1 t lbkhoz1 t1 t3 input signals: lad[0:31]/ldp[0:3] upm mode output signals: lcs [0:7]/lbs [0:3]/lgpl[0:5] gpcm mode output signals: lcs [0:7]/lwe t lbkhov1 t lbkhov1 t lbkhoz1 gpcm mode input signal: lgta
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 freescale semiconductor 49 local bus figure 29. local bus signals, gpcm/upm signals for lcrr[clkdiv] = 2 (clock ratio of 4) (pll bypass mode) t lbivkh1 t lbixkl2 internal launch/capture clock upm mode input signal: lupwait t1 t3 input signals: lad[0:31]/ldp[0:3] upm mode output signals: lcs [0:7]/lbs [0:3]/lgpl[0:5] gpcm mode output signals: lcs [0:7]/lwe t lbklov1 t lbkloz1 lclk t lbklox1 t lbixkh1 gpcm mode input signal: lgta t lbivkl2
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 50 freescale semiconductor local bus figure 30. local bus signals, gpcm/upm signals for lcrr[clkdiv] = 4 or 8 (clock ratio of 8 or 16) (pll enabled) lsync_in upm mode input signal: lupwait t lbixkh2 t lbivkh2 t lbivkh1 t lbixkh1 t lbkhoz1 t1 t3 upm mode output signals: lcs [0:7]/lbs [0:3]/lgpl[0:5] gpcm mode output signals: lcs [0:7]/lwe t lbkhov1 t lbkhov1 t lbkhoz1 t2 t4 input signals: lad[0:31]/ldp[0:3] gpcm mode input signal: lgta
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 freescale semiconductor 51 local bus figure 31. local bus signals, gpcm/upm signals for lcrr[clkdiv] = 4 or 8 (clock ratio of 8 or 16) (pll bypass mode) t lbixkl2 t lbivkh1 internal launch/capture clock upm mode input signal: lupwait t1 t3 upm mode output signals: lcs [0:7]/lbs [0:3]/lgpl[0:5] gpcm mode output signals: lcs [0:7]/lwe t2 t4 input signals: lad[0:31]/ldp[0:3] lclk t lbklov1 t lbkloz1 t lbklox1 t lbixkh1 gpcm mode input signal: lgta t lbivkl2
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 52 freescale semiconductor jtag 11 jtag this section describes the dc and ac electrical sp ecifications for the ieee 1149.1 (jtag) interface of the mpc8640/d. 11.1 jtag dc electrical characteristics table 43 provides the dc electrical characteristics for the jtag interface. 11.2 jtag ac electrical specifications table 44 provides the jtag ac timing specifications as defined in figure 33 through figure 35 . table 43. jtag dc electrical characteristics parameter symbol min max unit high-level input voltage v ih 2ov dd + 0.3 v low-level input voltage v il ?0.3 0.8 v input current (v in 1 = 0 v or v in = v dd) i in ?5 a high-level output voltage (ov dd = min, i oh = ?100 a) v oh ov dd ? 0.2 ? v low-level output voltage (ov dd = min, i ol = 100 a) v ol ?0.2 v note: 1. note that the symbol v in , in this case, represents the ov in symbol referenced in ta ble 1 and tab le 2 . table 44. jtag ac timing specifications (independent of sysclk) 1 at recommended operating conditions (see ta b l e 3 ). parameter symbol 2 min max unit notes jtag external clock frequency of operation f jtg 0 33.3 mhz ? jtag external clock cycle time t jtg 30 ? ns ? jtag external clock pulse width measured at 1.4 v t jtkhkl 15 ? ns ? jtag external clock rise and fall times t jtgr & t jtgf 02ns6 trst assert time t trst 25 ? ns 3 input setup times: boundary-scan data tms, tdi t jtdvkh t jtivkh 4 0 ? ? ns 4 input hold times: boundary-scan data tms, tdi t jtdxkh t jtixkh 20 25 ? ? ns 4 valid times: boundary-scan data tdo t jtkldv t jtklov 4 4 20 25 ns 5
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 freescale semiconductor 53 jtag figure 32 provides the ac test load for tdo and the boundary-scan outputs. figure 32. ac test load for the jtag interface figure 33 provides the jtag clock input timing diagram. figure 33. jtag clock input timing diagram output hold times: boundary-scan data tdo t jtkldx t jtklox 30 30 ? ? ns 5, 6 jtag external clock to output high impedance: boundary-scan data tdo t jtkldz t jtkloz 3 3 19 9 ns 5, 6 notes: 1. all outputs are measured from the midpoint voltage of the falling/rising edge of t tclk to the midpoint of the signal in question. the output timings are measured at the pins. all output timings assume a purely resistive 50- load (see figure 32 ). time-of-flight delays must be added for trace lengths, vias, and connectors in the system. 2. the symbols used for timing specifications herein follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t jtdvkh symbolizes jtag device timing (jt) with respect to the time data input signals (d) reaching the valid state (v) relative to the t jtg clock reference (k) going to the high (h) state or setup time. also, t jtdxkh symbolizes jtag timing (jt) with respect to the time data input signals (d) went invalid (x) relative to the t jtg clock reference (k) going to the high (h) state. note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). 3. trst is an asynchronous level sensitive signal. the setup time is for test purposes only. 4. non-jtag signal input timing with respect to t tclk . 5. non-jtag signal output timing with respect to t tclk . 6. guaranteed by design. table 44. jtag ac timing specifications (independent of sysclk) 1 (continued) at recommended operating conditions (see ta b l e 3 ). parameter symbol 2 min max unit notes output z 0 = 50 ov dd /2 r l = 50 jtag t jtkhkl t jtgr external clock vm vm vm t jtg t jtgf vm = midpoint voltage (ov dd /2)
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 54 freescale semiconductor i 2 c figure 34 provides the trst timing diagram. figure 34. trst timing diagram figure 35 provides the boundary-scan timing diagram. figure 35. boundary-scan timing diagram 12 i 2 c this section describes the dc and ac electrical characteristics for the i 2 c interfaces of the mpc8640. 12.1 i 2 c dc electrical characteristics table 45 provides the dc electrical characteristics for the i 2 c interfaces. table 45. i 2 c dc electrical characteristics at recommended operating conditions with ov dd of 3.3 v 5%. parameter symbol min max unit notes input high voltage level v ih 0.7 ov dd ov dd +0.3 v ? input low voltage level v il ?0.3 0.3 ov dd v? low level output voltage v ol 00.2 ov dd v1 pulse width of spikes which must be suppressed by the input filter t i2khkl 050ns2 trst vm = midpoint voltage (ov dd /2) vm vm t trst vm = midpoint voltage (ov dd /2) vm vm t jtdvkh t jtdxkh boundary data outputs boundary data outputs jtag external clock boundary data inputs output data valid t jtkldx t jtkldz t jtkldv input data valid output data valid
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 freescale semiconductor 55 i 2 c 12.2 i 2 c ac electrical specifications table 46 provides the ac timing parameters for the i 2 c interfaces. input current each i/o pin (input voltage is between 0.1 ov dd and 0.9 ov dd (max) i i ?10 10 a3 capacitance for each i/o pin c i ?10pf? notes: 1. output voltage (open drain or open collector) condition = 3 ma sink current. 2. refer to the mpc8641 integrated host processor reference manual for information on the digital filter used. 3. i/o pins will obstruct the sda and scl lines if ov dd is switched off. table 46. i 2 c ac electrical specifications all values refer to v ih (min) and v il (max) levels (see table 45 ). parameter symbol 1 min max unit scl clock frequency f i2c 0 400 khz low period of the scl clock t i2cl 4 1.3 ? s high period of the scl clock t i2ch 4 0.6 ? s setup time for a repeated start condition t i2svkh 4 0.6 ? s hold time (repeated) start condition (after this period, the first clock pulse is generated) t i2sxkl 4 0.6 ? s data setup time t i2dvkh 4 100 ? ns data input hold time: cbus compatible masters i 2 c bus devices t i2dxkl ? 0 2 ? ? s rise time of both sda and scl signals t i2cr 20 + 0.1 c b 5 300 ns fall time of both sda and scl signals t i2cf 20 + 0.1 c b 5 300 ns data output delay time t i2ovkl ?0.9 3 s set-up time for stop condition t i2pvkh 0.6 ? s bus free time between a stop and start condition t i2khdx 1.3 ? s noise margin at the low level for each connected device (including hysteresis) v nl 0.1 ov dd ?v table 45. i 2 c dc electrical characteristics (continued) at recommended operating conditions with ov dd of 3.3 v 5%. parameter symbol min max unit notes
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 56 freescale semiconductor i 2 c figure 32 provides the ac test load for the i 2 c. figure 36. i 2 c ac test load noise margin at the high level for each connected device (including hysteresis) v nh 0.2 ov dd ?v note: 1. the symbols used for timing specifications herein follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t i2dvkh symbolizes i 2 c timing (i2) with respect to the time data input signals (d) reach the valid state (v) relative to the t i2c clock reference (k) going to the high (h) state or setup time. also, t i2sxkl symbolizes i 2 c timing (i2) for the time that the data with respect to the start condition (s) went invalid (x) relative to the t i2c clock reference (k) going to the low (l) state or hold time. also, t i2pvkh symbolizes i 2 c timing (i2) for the time that the data with respect to the stop condition (p) reaching the valid state (v) relative to the t i2c clock reference (k) going to the high (h) state or setup time. for rise and fall times, the latter convention is used with the approp riate letter: r (rise) or f (fall). 2. as a transmitter, the mpc8640 provides a delay time of at least 300 ns for the sda signal (referred to the vihmin of the scl signal) to bridge the undefined region of the falling edge of scl to avoid unintended generation of start or stop condition. when mpc8640 acts as the i 2 c bus master while transmitting, mpc8640 drives both scl and sda. as long as the load on scl and sda are balanced, mpc8640 would not cause unintended generation of start or stop condition. therefore, the 300 ns sda output delay time is not a concern. if, under some rare condition, the 300 ns sda output delay time is required for mpc8640 as transmitter, the following setting is recommended for the fdr bit field of the i2cfdr register to ensure both the desired i 2 c scl clock frequency and sda output delay time are achieved, assuming that the desired i 2 c scl clock frequency is 400 khz and the digital filter sampling rate register (i2cdfsrr) is programmed with its default setting of 0x10 (decimal 16): i 2 c source clock frequency 333 mhz 266 mhz 200 mhz 133 mhz fdr bit setting 0x2a 0x05 0x26 0x00 actual fdr divider selected 896 704 512 384 actual i 2 c scl frequency generated 371 khz 378 khz 390 khz 346 khz for the detail of i 2 c frequency calculation, refer to the application note an2919 ?determining the i 2 c frequency divider ratio for scl.? note that the i 2 c source clock frequency is half of the mpx clock frequency for mpc8640. 3. the maximum t i2dxkl has only to be met if the device does not stretch the low period (t i2cl ) of the scl signal. 4. guaranteed by design. 5. c b = capacitance of one bus line in pf. table 46. i 2 c ac electrical specifications (continued) all values refer to v ih (min) and v il (max) levels (see table 45 ). parameter symbol 1 min max unit output z 0 = 50 ov dd /2 r l = 50
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 freescale semiconductor 57 high-speed serial interfaces (hssi) figure 37 shows the ac timing diagram for the i 2 c bus. figure 37. i 2 c bus ac timing diagram 13 high-speed serial interfaces (hssi) the mpc8640d features two serializer/deserializer (serde s) interfaces to be used for high-speed serial interconnect applications. the serdes1 interface is de dicated for pci express data transfers. the serdes2 can be used for pci express and/or serial rapidio data transfers. this section describes the common portion of serdes dc electrical specifications, which is the dc requirement for serdes reference clocks. the serdes data lane?s transmitter and receiver reference circuits are also shown. 13.1 signal terms definition the serdes utilizes differential signaling to transfer data across the serial link. this section defines terms used in the description and specification of differential signals. sr s sda scl t i2cf t i2sxkl t i2cl t i2ch t i2dxkl t i2dvkh t i2sxkl t i2svkh t i2khkl t i2pvkh t i2cr t i2cf ps
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 58 freescale semiconductor high-speed serial interfaces (hssi) figure 38 shows how the signals are defined. for illustration purpose, only one serdes lane is used for description. the figure shows waveform for either a transmitter output (sd n _tx and sd n _tx ) or a receiver input (sd n _rx and sd n _rx ). each signal swings between a volts and b volts where a > b. figure 38. differential voltage definitions for transmitter or receiver using this waveform, the definitions are as follows. to simplify illustration, the following definitions assume that the serdes transmitter and receiver opera te in a fully symmetrical differential signaling environment. single-ended swing the transmitter output signals and the receiver input signals sd n _tx, sd n _tx , sd n _rx and sd n _rx each have a peak-to-peak swing of a ? b volts. this is also referred as each signal wire?s single-ended swing. differential output voltage, v od (or differential output swing ): the differential output voltage (or swing) of the transmitter, v od , is defined as the difference of the two complimentary output voltages: v sd n _tx ? v sd n _tx . the v od value can be either positive or negative. differential input voltage, v id (or differential input swing ): the differential input voltage (or swing) of the receiver, v id , is defined as the difference of the two complimentary input voltages: v sd n _rx ? v sd n _rx . the v id value can be either positive or negative. differential peak voltage , v diffp the peak value of the differential transmitter output signal or the differential receiver input signal is defined as differential peak voltage, v diffp = |a ? b| volts. differential peak-to-peak , v diffp-p since the differential output signal of the transmitter and the differential input signal of the receiver each range from a ? b to ?(a ? b) volts, the peak-to-peak value of the differential transmitter output signal or the differential receiver input differential swing, vid or vod = a ? b a volts b volts sdn_tx or sdn_rx sdn_tx or sdn_rx differential peak voltage, vdiffp = |a - b| differential peak-peak voltage, vdiffpp = 2 vdiffp (not shown) v cm = (a + b) 2
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 freescale semiconductor 59 high-speed serial interfaces (hssi) signal is defined as differential peak-to-peak voltage, v diffp-p =2 v diffp =2 |(a ? b)| volts, which is twice of differential swing in amplitude, or twice of the differential peak. for example, the output differential peak-peak voltage can also be calculated as v tx-diffp-p = 2 |v od |. differential waveform the differential waveform is construc ted by subtracting the inverting signal (sd n _tx , for example) from the non-inverting signal (sd n _tx, for example) within a differential pair. there is only one signal trace curve in a differential waveform. the voltage represented in the differential waveform is not referenced to ground. refer to figure 47 as an example for differential waveform. common mode voltage, v cm the common mode voltage is equal to one half of the sum of the voltages between each conductor of a balanced interchange ci rcuit and ground. in this example, for serdes output, v cm_out = (v sd n _tx + v sd n _tx ) 2 = (a + b) 2, which is the arithmetic mean of the two complimentary output voltages within a differential pair. in a system, the common mode voltage may often differ from one component?s output to the other?s input. sometimes, it may be even different between the receiver input and driver output circuits within the same component. it is also referred as the dc offset in some occasion. to illustrate these definitions using real values, consider the case of a current mode logic (cml) transmitter that has a common mode voltage of 2.25 v and each of its outputs, td and td , has a swing that goes between 2.5 v and 2.0 v. us ing these values, the peak-to-peak voltage swing of each signal (td or td ) is 500 mv p-p, which is referred as the single-ended swing for each signal. in this example, since the differential signaling environment is fully symmetrical, the transmitter output?s differential swing (v od ) has the same amplitude as each signal?s single-ended swing. the differential output signal ranges between 500 mv and ?500 mv, in other words, v od is 500 mv in one phase and ?500 mv in the other phase. the peak differential voltage (v diffp ) is 500 mv. the peak-to-peak differential voltage (v diffp-p ) is 1000 mv p-p. 13.2 serdes reference clocks the serdes reference clock inputs are applied to an internal pll whose output creates the clock used by the corresponding serdes lanes. the serdes reference clocks inputs are sd n _ref_clk and sd n _ref_clk for pci express and serial rapidio. the following sections describe the serdes re ference clock requirement s and some application information.
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 60 freescale semiconductor high-speed serial interfaces (hssi) 13.2.1 serdes reference clock receiver characteristics figure 39 shows a receiver reference diagram of the serdes reference clocks. ? the supply voltage requirements for xv dd_ srds n are specified in table 1 and table 2 . ? serdes reference clock receiver reference circuit structure ?the sd n _ref_clk and sd n _ref_clk are internally ac-coupled differential inputs as shown in figure 39 . each differential clock input (sd n _ref_clk or sd n _ref_clk ) has a 50- termination to sgnd followed by on-chip ac-coupling. ? the external reference clock driver must be able to drive this termination. ? the serdes reference clock input can be eith er differential or single-ended. refer to the differential mode and single-ended mode descri ption below for further detailed requirements. ? the maximum average current requirement that also determines the common mode voltage range ? when the serdes reference clock differential i nputs are dc coupled externally with the clock driver chip, the maximum average current allowed for each input pin is 8 ma. in this case, the exact common mode input voltage is not critical as long as it is within the range allowed by the maximum average current of 8 ma (refer to th e following bullet for more detail), since the input is ac-coupled on-chip. ? this current limitation sets the maximum common m ode input voltage to be less than 0.4 v (0.4 v 50 = 8 ma) while the minimum common mode input level is 0.1 v above sgnd. for example, a clock with a 50/50 duty cycle can be produced by a clock driver with output driven by its current source from 0 ma to 16 ma (0?0.8 v), such that each phase of the differential input has a single-ended swing from 0 v to 800 mv with the common mode voltage at 400 mv. ? if the device driving the sd n _ref_clk and sd n _ref_clk inputs cannot drive 50 to sgnd dc, or it exceeds the maximum input current limitations, then it must be ac-coupled off-chip. ? the input amplitude requirement ? this requirement is described in detail in the following sections. figure 39. receiver of serdes reference clocks input amp 50 w 50 w sd n _ref_clk sd n _ref_clk
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 freescale semiconductor 61 high-speed serial interfaces (hssi) 13.2.2 dc level requirement for serdes reference clocks the dc level requirement for the mpc8640d serdes reference clock inputs is different depending on the signaling mode used to connect the clock driver ch ip and serdes reference clock inputs as described below. ? differential mode ? the input amplitude of the differential clock must be between 400 mv and 1600 mv differential peak-peak (or between 200 mv and 800 mv differential peak). in other words, each signal wire of the differential pair must have a single-ended swing less than 800 mv and greater than 200 mv. this requirement is the same for both external dc-coupled or ac-coupled connection. ? for external dc-coupled connection, as described in section 13.2.1 , the maximum average current requirements sets the requirement for average voltage (common mode voltage) to be between 100 mv and 400 mv. figure 40 shows the serdes reference clock input requirement for dc-coupled connection scheme. ? for external ac-coupled connection, there is no common m ode voltage requirement for the clock driver. since the external ac-coupling capac itor blocks the dc level, the clock driver and the serdes reference clock receiver operate in different command mode voltages. the serdes reference clock receiver in this connec tion scheme has its common mode voltage set to sgnd. each signal wire of the differential i nputs is allowed to swing below and above the command mode voltage (sgnd). figure 41 shows the serdes reference clock input requirement for ac-coupled connection scheme. ? single-ended mode ? the reference clock can also be single-ended. the sd n _ref_clk input amplitude (single-ended swing) must be between 400 mv and 800 mv peak-peak (from v min to v max ) with sd n _ref_clk either left unconnected or tied to ground. ?the sd n _ref_clk input average voltage must be between 200 and 400 mv. figure 42 shows the serdes reference clock input requirement for single-ended signaling mode. ? to meet the input amplitude requirement, the re ference clock inputs might need to be dc or ac-coupled externally. for the best noise performance, the reference of the clock could be dc or ac-coupled into the unused phase (sd n _ref_clk ) through the same source impedance as the clock input (sd n _ref_clk) in use. figure 40. differential reference clock input dc requirements (external dc-coupled) sd n _ref_clk sd n _ref_clk vmax < 800mv vmin > 0v 100mv < vcm < 400mv 200mv < input amplitude or differential peak < 800mv
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 62 freescale semiconductor high-speed serial interfaces (hssi) figure 41. differential reference clock input dc requirements (external ac-coupled) figure 42. single-ended reference clock input dc requirements 13.2.3 interfacing with other differential signaling levels the following list explains characteristics of in terfacing with other differential signaling levels. ? with on-chip termination to sgnd, the differentia l reference clocks inputs are hcsl (high-speed current steering logic) compatible dc-coupled. ? many other low voltage differential type outputs li ke lvds (low voltage differential signaling) can be used but may need to be ac-coupled due to the limited common mode input range allowed (100 to 400 mv) for dc-coupled connection. ? lvpecl outputs can produce signal with too large amplitude. it may need to be dc-biased at clock driver output first and followed with series attenuation resistor to reduce the amplitude, in addition to ac-coupling. sd n _ref_clk sd n _ref_clk vcm 200mv < input amplitude or differential peak < 800mv vmax < vcm + 400 mv vmin > vcm ? 400 mv sd n _ref_clk sd n _ref_clk 400 mv < sd n _ref_clk input amplitude < 800 mv 0v
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 freescale semiconductor 63 high-speed serial interfaces (hssi) figure 43 shows the serdes reference clock connection reference circuits for hcsl type clock driver. it assumes that the dc levels of the clock driver chip is compatible with mpc8640d serdes reference clock input?s dc requirement. note figure 43 ? figure 46 are for conceptual reference only. due to the differences in the clock driver chip?s internal structure, output impedance, and termination requirements among various clock driver chip manufacturers, the clock circuit reference designs provided by clock driver chip vendor may be different from what is shown above. they may also vary from one vendor to the other. therefore, freescale semiconductor can neither provide the optimal clock driver reference circuits, nor guarantee the correctness of the following clock driver connection reference circuits. the system designer is recommended to cont act the selected clock driver chip vendor for the optimal reference circuits with the mpc8640d serdes reference clock receiver requirement provided in this document. figure 43. dc-coupled differential connection with hcsl clock driver (reference only) figure 44 shows the serdes reference clock connection reference circuits for lvds type clock driver. since lvds clock driver?s common mode voltage is higher than the mpc8640d serdes reference clock input?s allowed range (100 to 400mv), ac-coupled connection scheme must be used. it assumes the 50 50 sd n _ref_clk sd n _ref_clk clock driver 100 differential pwb trace clock driver vendor dependent source termination resistor serdes refer. clk receiver clock driver clk_out clk_out hcsl clk driver chip 33 33 total 50 . assume clock driver?s output impedance is about 16 . mpc8640d clk_out
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 64 freescale semiconductor high-speed serial interfaces (hssi) lvds output driver features 50- termination resistor. it also assumes that the lvds transmitter establishes its own common mode level without rely ing on the receiver or other external component. figure 44. ac-coupled differential connection with lvds clock driver (reference only) figure 45 shows the serdes reference clock connection refe rence circuits for lvpecl type clock driver. since lvpecl driver?s dc levels (both common mode voltages and output swing) are incompatible with mpc8640d serdes reference clock input?s dc requirement, ac-coupling has to be used. figure 45 assumes that the lvpecl clock driver?s output impedance is 50 . r1 is used to dc-bias the lvpecl outputs prior to ac-coupling. its value could be ranged from 140 to 240 depending on clock driver vendor?s requirement. r2 is used together with the serdes reference clock receiver?s 50- termination resistor to attenuate the lvpecl output?s differential peak level such that it meets the mpc8640d serdes reference clock?s differential input amplitude re quirement (between 200 mv and 800 mv differential peak). for example, if the lvpecl output?s differential peak is 900 mv and the desired serdes reference clock input amplitude is selected as 600 mv, the attenuation factor is 0.67, which requires r2 = 25 . 50 50 sd n _ref_clk sd n _ref_clk clock driver 100 differential pwb trace serdes refer. clk receiver clock driver clk_out clk_out lvds clk driver chip 10 nf 10 nf mpc8640d
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 freescale semiconductor 65 high-speed serial interfaces (hssi) please consult with the clock driver chip manufactur er to verify whether th is connection scheme is compatible with a particular clock driver chip. figure 45. ac-coupled differential connection with lvpecl clock driver (reference only) figure 46 shows the serdes reference clock connection refe rence circuits for a single-ended clock driver. it assumes the dc levels of the clock driver ar e compatible with mpc8640d serdes reference clock input?s dc requirement. figure 46. single-ended connection (reference only) 13.2.4 ac requirements for serdes reference clocks the clock driver selected should provide a high quality reference clock with low phase noise and cycle-to-cycle jitter. phase noise less than 100 khz can be tracked by the pll and data recovery loops and is less of a problem. phase noise above 15 mhz is f iltered by the pll. the most problematic phase noise 50 50 sd n _ref_clk sd n _ref_clk clock driver 100 differential pwb trace serdes refer. clk receiver clock driver clk_out clk_out lvpecl clk driver chip r2 r2 r1 mpc8640d r1 10nf 10nf 10nf 50 50 sd n _ref_clk sd n _ref_clk 100 differential pwb trace serdes refer. clk receiver clock driver clk_out single-ended clk driver chip mpc8640d 33 tot a l 50 . assume clock driver?s output impedance is about 16 . 50
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 66 freescale semiconductor high-speed serial interfaces (hssi) occurs in the 1?15 mhz range. the source impedance of the clock driver should be 50 to match the transmission line and reduce reflections which are a source of noise to the system. table 47 describes some ac parameters common to pci express and serial rapidio protocols. figure 47. differential measurement points for rise and fall time table 47. serdes reference clock common ac parameters at recommended operating conditions with xv dd_ srds1 or xv dd_ srds2 = 1.1 v 5% and 1.05 v 5%. parameter symbol min max unit notes rising edge rate rise edge rate 1.0 4.0 v/ns 2, 3 falling edge rate fall edge rate 1.0 4.0 v/ns 2, 3 differential input high voltage v ih +200 ? mv 2 differential input low voltage v il ? ?200 mv 2 rising edge rate (sd n _ref_clk) to falling edge rate (sd n _ref_clk ) matching rise-fall matching ?20%1, 4 notes: 1. measurement taken from single-ended waveform. 2. measurement taken from differential waveform. 3. measured from ?200 mv to +200 mv on the differential waveform (derived from sd n _ref_clk minus sd n _ref_clk ). the signal must be monotonic through the measurement region for rise and fall time. the 400 mv measurement window is centered on the differential zero crossing. see figure 47 . 4. matching applies to the rising edge rate for sd n _ref_clk and falling edge rate for sd n _ref_clk . it is measured using a 200 mv window centered on the median cross point where sdn_ref_clk rising meets sd n _ref_clk falling. the median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. the rising e dge rate of sd n _ref_clk should be compared to the falling edge rate of sd n _ref_clk , and the maximum allowed difference should not exceed 20% of the slowest edge rate. see figure 48 . v ih = +200 mv v il = ?200 mv 0.0 v sd n _ref_clk minus sd n _ref_clk
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 freescale semiconductor 67 high-speed serial interfaces (hssi) figure 48. single-ended measurement points for rise and fall time matching the other detailed ac requirements of the serdes refe rence clocks is defined by each interface protocol based on application usage. refer to the following sections for detailed information: ? section 14.2, ?ac requirements for pci express serdes clocks ? ? section 15.2, ?ac requirements for serial rapidio sdn_ref_clk and sdn_ref_clk ? 13.3 serdes transmitter and receiver reference circuits figure 49 shows the reference circuits for serdes data lane?s transmitter and receiver. figure 49. serdes transmitter and receiver reference circuits the dc and ac specification of serdes data lanes ar e defined in each interface protocol section below (pci express or serial rapid io) in this document based on the application usage: ? section 14, ?pci express? ? section 15, ?serial rapidio? note that external ac coupling capacitor is required for the above two serial transmission protocols with the capacitor value defined in specification of each protocol section. sd n _ref_clk sd n _ref_clk sd n _ref_clk sd n _ref_clk 50 50 receiver transmitter sd1_tx n or sd2_tx n sd1_tx n or sd2_tx n sd1_rx n or sd2_rx n sd1_rx n or sd2_rx n 50 50
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 68 freescale semiconductor pci express 14 pci express this section describes the dc and ac electrical specifications for the pci express bus of the mpc8640. 14.1 dc requirements for pci express sd n _ref_clk and sd n _ref_clk for more information, see section 13.2, ?serdes reference clocks.? 14.2 ac requirements for pci express serdes clocks table 48 lists ac requirements. 14.3 clocking dependencies the ports on the two ends of a link must transmit data at a rate that is within 600 parts per million (ppm) of each other at all times. this is specified to a llow bit rate clock sources with a 300 ppm tolerance. 14.4 physical layer specifications the following is a summary of the specifications for the physical layer of pci express on this device. for further details as well as the specifications of the transport and data link layer please use the pci express base specification, rev. 1.0a document. 14.4.1 differential transmitter (tx) output table 49 defines the specifications for the differential output at all transmitters. the parameters are specified at the component pins. table 48. sd n _ref_clk and sd n _ref_clk ac requirements parameter symbol min typical max units notes refclk cycle time t ref ?10 ?ns ? refclk cycle-to-cycle jitter. difference in the period of any two adjacent refclk cycles t refcj ??100ps ? phase jitter. deviation in edge location with respect to mean edge location t refpj ?50 ? 50 ps ? table 49. differential transmitter output specifications parameter symbol min nom max units notes unit interval ui 399.88 400 400.12 ps each ui is 400 ps 300 ppm. ui does not account for spread spectrum clock dictated variations. see note 1. differential peak-to-peak output voltage v tx-diffp-p 0.8 ? 1.2 v v tx-diffp-p = 2 |v tx-d+ ?v tx-d- | see note 2.
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 freescale semiconductor 69 pci express de- emphasized differential output voltage (ratio) v tx-de-ratio ?3.0 ?3.5 ?4.0 db ratio of the v tx-diffp-p of the second and following bits after a transition divided by the v tx-diffp-p of the first bit after a transition. see note 2. minimum tx eye width t tx-eye 0.70 ? ? ui the maximum transmitter jitter can be derived as t tx-max-jitter = 1 ? t tx-eye = 0.3 ui. see notes 2 and 3. maximum time between the jitter median and maximum deviation from the median. t tx-eye-median-to- max-jitter ? ? 0.15 ui jitter is defined as the measurement variation of the crossing points (v tx-diffp-p = 0 v) in relation to a recovered tx ui. a recovered tx ui is calculated over 3500 consecutive unit intervals of sample data. jitter is measured using all edges of the 250 consecutive ui in the center of the 3500 ui used for calculating the tx ui. see notes 2 and 3. d+/d? tx output rise/fall time t tx-rise , t tx-fall 0.125 ? ? ui see notes 2 and 5 rms ac peak common mode output voltage v tx-cm-acp ??20mvv tx-cm-acp = rms(|v txd+ + v txd- |/2 ? v tx-cm-dc ) v tx-cm-dc = dc (avg) of |v tx-d+ + v tx-d? |/2 see note 2 absolute delta of dc common mode voltage during l0 and electrical idle v tx-cm-dc-active- idle-delta 0 ? 100 mv |v tx-cm-dc (during l0) ? v tx-cm-idle-dc (during electrical idle) | 100 mv v tx-cm-dc = dc (avg) of |v tx-d+ + v tx-d- |/2 [l0] v tx-cm-idle-dc = dc (avg) of |v tx-d+ + v tx-d? |/2 [electrical idle] see note 2. absolute delta of dc common mode between d+ and d? v tx-cm-dc-line-delta 0?25mv|v tx-cm-dc-d+ ? v tx-cm-dc-d- | 25 mv v tx-cm-dc-d+ = dc (avg) of |v tx-d+ | v tx-cm-dc-d? = dc (avg) of |v tx-d? | see note 2. electrical idle differential peak output voltage v tx-idle-diffp 0?20mvv tx-idle-diffp = |v tx-idle-d+ -v tx-idle-d? | 20 mv see note 2. the amount of voltage change allowed during receiver detection v tx-rcv-detect ? ? 600 mv the total amount of voltage change that a transmitter can apply to sense whether a low impedance receiver is present. see note 6. the tx dc common mode voltage v tx-dc-cm 0 ? 3.6 v the allowed dc common mode voltage under any conditions. see note 6. tx short circuit current limit i tx-short ? 90 ma the total current the transmitter can provide when shorted to its ground minimum time spent in electrical idle t tx-idle-min 50 ? ui minimum time a transmitter must be in electrical idle. utilized by the receiver to start looking for an electrical idle exit after successfully receiving an electrical idle ordered set. table 49. differential transmitter output specifications (continued) parameter symbol min nom max units notes
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 70 freescale semiconductor pci express maximum time to transition to a valid electrical idle after sending an electrical idle ordered set t tx-idle-set-to-idle ? ? 20 ui after sending an electrical idle ordered set, the transmitter must meet all electrical idle specifications within this time. this is considered a debounce time for the transmitter to meet electrical idle after transitioning from l0. maximum time to transition to valid tx specifications after leaving an electrical idle condition t tx-idle-to-diff-data ? ? 20 ui maximum time to meet all tx specifications when transitioning from electrical idle to sending differential data. this is considered a debounce time for the tx to meet all tx specifications after leaving electrical idle differential return loss rl tx-diff 12 ? ? db measured over 50 mhz to 1.25 ghz. see note 4 common mode return loss rl tx-cm 6 ? ? db measured over 50 mhz to 1.25 ghz. see note 4 dc differential tx impedance z tx-diff-dc 80 100 120 tx dc differential mode low impedance transmitter dc impedance z tx-dc 40 ? ? required tx d+ as well as d? dc impedance during all states lane-to-lane output skew l tx-skew ? ? 500 + 2 ui ps static skew between any two transmitter lanes within a single link ac coupling capacitor c tx 75 ? 200 nf all transmitters shall be ac coupled. the ac coupling is required either within the media or within the transmitting component itself. see note 8. crosslink random timeout t crosslink 0 ? 1 ms this random timeout helps resolve conflicts in crosslink configuration by eventually resulting in only one downstream and one upstream port. see note 7. notes: 1. no test load is necessarily associated with this value. 2. specified at the measurement point into a timing and voltage compliance test load as shown in figure 52 and measured over any 250 consecutive tx uis. (also refer to the transmitter compliance eye diagram shown in figure 50 ) 3. a t tx-eye = 0.70 ui provides for a total sum of deterministic and random jitter budget of t tx-jitter-max = 0.30 ui for the transmitter collected over any 250 consecutive tx uis. the t tx-eye-median-to-max-jitter median is less than half of the total tx jitter budget collected over any 250 consecutive tx uis. it should be noted that the median is not the same as the mean. the jitter median describes the point in time where the number of jitter points on either side is approximately equal as oppose d to the averaged time value. 4. the transmitter input impedance shall result in a differential return loss greater than or equal to 12 db and a common mode return loss greater than or equal to 6 db over a frequency range of 50 mhz to 1.25 ghz. this input impedance requirement applies to all valid input levels. the reference impedance for return loss measurements is 50 to ground for both the d+ and d? line (that is, as measured by a vector network analyzer with 50 probes?see figure 52 ). note that the series capacitors c tx is optional for the return loss measurement. 5. measured between 20?80% at transmitter package pins into a test load as shown in figure 52 for both v tx-d+ and v tx-d? . 6. see section 4.3.1.8 of the pci express base specifications rev 1.0a 7. see section 4.2.6.3 of the pci express base specifications rev 1.0a 8. mpc8640d serdes transmitter does not have c tx built-in. an external ac coupling capacitor is required. table 49. differential transmitter output specifications (continued) parameter symbol min nom max units notes
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 freescale semiconductor 71 pci express 14.4.2 transmitter compliance eye diagrams the tx eye diagram in figure 50 is specified using the passive compliance/test measurement load (see figure 52 ) in place of any real pci express interconnect + rx component. there are two eye diagrams that must be met for the transmitter. both eye diagrams must be aligned in time using the jitter median to locate the center of the eye diagram. the different eye diagrams will differ in voltage depending whether it is a transition bit or a de-emphasized bit. the exact reduced voltage level of the de-emphasized bit will always be relative to the transition bit. the eye diagram must be valid for any 250 consecutive uis. a recovered tx ui is calculated over 3500 consecutive unit intervals of sample data. the eye diagram is created using all edges of the 250 consecutive ui in the center of the 3500 ui used for calculating the tx ui. note it is recommended that the recovered tx ui is calculated using all edges in the 3500 consecutive ui interval with a fit algorithm using a minimization merit function (that is, least squa res and median deviation fits). figure 50. minimum transmitter timing and voltage output compliance specifications
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 72 freescale semiconductor pci express 14.4.3 differential receiver (rx) input specifications table 50 defines the specifications for the differential input at all receivers. the parameters are specified at the component pins. table 50. differential receiver input specifications parameter symbol min nom max units comments unit interval ui 399.88 400 400.12 ps each ui is 400 ps 300 ppm. ui does not account for spread spectrum clock dictated variations. see note 1. differential peak-to-peak output voltage v rx-diffp-p 0.175 ? 1.200 v v rx-diffp-p = 2 |v rx-d+ ? v rx-d? | see note 2. minimum receiver eye width t rx-eye 0.4 ? ? ui the maximum interconnect media and transmitter jitter that can be tolerated by the receiver can be derived as t rx-max-jitter = 1 ? t rx-eye = 0.6 ui. see notes 2 and 3. maximum time between the jitter median and maximum deviation from the median. t rx-eye-median-to-max -jitter ? ? 0.3 ui jitter is defined as the measurement variation of the crossing points (v rx-diffp-p = 0 v) in relation to a recovered tx ui. a recovered tx ui is calculated over 3500 consecutive unit intervals of sample data. jitter is measured using all edges of the 250 consecutive ui in the center of the 3500 ui used for calculating the tx ui. see notes 2, 3 and 7. ac peak common mode input voltage v rx-cm-acp ??150 mvv rx-cm-acp = |v rxd+ ? v rxd- |/2 ? v rx-cm-dc v rx-cm-dc = dc (avg) of |v rx-d+ ? v rx-d? |/2 see note 2 differential return loss rl rx-diff 15 ? ? db measured over 50 mhz to 1.25 ghz with the d+ and d? lines biased at +300 mv and ?300 mv, respectively. see note 4 common mode return loss rl rx-cm 6 ? ? db measured over 50 mhz to 1.25 ghz with the d+ and d? lines biased at 0 v. see note 4 dc differential input impedance z rx-diff-dc 80 100 120 rx dc differential mode impedance. see note 5 dc input impedance z rx-dc 40 50 60 required rx d+ as well as d? dc impedance (50 20% tolerance). see notes 2 and 5. powered down dc input impedance z rx-high-imp-dc 200 ? ? k required rx d+ as well as d? dc impedance when the receiver terminations do not have power. see note 6. electrical idle detect threshold v rx-idle-det-diffp-p 65 ? 175 mv v rx-idle-det-diffp-p = 2 |v rx-d+ ?v rx-d? | measured at the package pins of the receiver
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 freescale semiconductor 73 pci express 14.5 receiver compliance eye diagrams the rx eye diagram in figure 51 is specified using the passive compliance/test measurement load (see figure 52 ) in place of any real pci express rx component. note that in general, the minimum receiver eye diagram measured with the compliance/test measurement load (see figure 52 ) is larger than the minimum receiver eye diagram measured over a range of systems at the input receiver of any real pci express component. the degraded eye diagram at the input receiver is due to traces internal to the package as well as silicon parasitic characteristics which cause the real pci express component to vary in impedance from the co mpliance/test measurement load. the input receiver eye diagram is implementation specific and is not specified. a rx component designer should provide unexpected electrical idle enter detect threshold integration time t rx-idle-det-diff- entertime ? ? 10 ms an unexpected electrical idle (v rx-diffp-p < v rx-idle-det-diffp-p ) must be recognized no longer than t rx-idle-det-diff-entering to signal an unexpected idle condition. tot a l s kew l tx-skew ? ? 20 ns skew across all lanes on a link. this includes variation in the length of skp ordered set (for example, com and one to five symbols) at the rx as well as any delay differences arising from the interconnect itself. notes: 1. no test load is necessarily associated with this value. 2. specified at the measurement point and measured over any 250 consecutive uis. the test load in figure 52 should be used as the rx device when taking measurements (also refer to the receiver compliance eye diagram shown in figure 51 ). if the clocks to the rx and tx are not derived from the same reference clock, the tx ui recovered from 3500 consecutive ui must be used as a reference for the eye diagram. 3. a t rx-eye = 0.40 ui provides for a total sum of 0.60 ui deterministic and random jitter budget for the transmitter and interconnect collected any 250 consecutive uis. the t rx-eye-median-to-max-jitter specification ensures a jitter distribution in which the median and the maximum deviation from the median is less than half of the total. ui jitter budget collected over any 250 consecutive tx uis. it should be noted that the median is not the same as the mean. the jitter median describes the point in time where the number of jitter points on either side is approximately equal as opposed to the averaged time value. if the clocks to the rx and tx are not derived from the same reference clock, the tx ui recovered from 3500 consecutive ui must be used as the reference for the eye diagram. 4. the receiver input impedance shall result in a differential return loss greater than or equal to 15 db with the d+ line bias ed to 300 mv and the d? line biased to ?300 mv and a common mode return loss greater than or equal to 6 db (no bias required) over a frequency range of 50 mhz to 1.25 ghz. this input impedance requirement applies to all valid input levels. the reference impedance for return loss measurements for is 50 to ground for both the d+ and d? line (that is, as measured by a vector network analyzer with 50- probes, see figure 52 ). note that the series capacitors c tx is optional for the return loss measurement. 5. impedance during all ltssm states. when transitioning from a fundamental reset to detect (the initial state of the ltssm) there is a 5 ms transition time before receiver termination values must be met on all unconfigured lanes of a port. 6. the rx dc common mode impedance that exists when no power is present or fundamental reset is asserted. this helps ensure that the receiver detect circuit will not falsely assume a receiver is powered on when it is not. this term must be measured at 300 mv above the rx ground. 7. it is recommended that the recovered tx ui is calculated using all edges in the 3500 consecutive ui interval with a fit algo rithm using a minimization merit function. least squares and median deviation fits have worked well with experimental and simulated data. table 50. differential receiver input specifications (continued) parameter symbol min nom max units comments
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 74 freescale semiconductor pci express additional margin to adequately compensate for the degraded minimum rx eye diagram (shown in figure 51 ) expected at the input receiver based on some ad equate combination of system simulations and the return loss measured looking into the rx package and silicon. the rx eye diagram must be aligned in time using the jitter median to locate the center of the eye diagram. the eye diagram must be valid for any 250 consecutive uis. a recovered tx ui is calculated over 3500 consecutive un it intervals of sample data. the eye diagram is created using all edges of the 250 consecutive ui in the center of the 3500 ui used for calculating the tx ui. note the reference impedance for return loss measurements is 50 to ground for both the d+ and d? line (that is, as measured by a vector network analyzer with 50- probes?see figure 52 ). note that the series capacitors, c tx , are optional for the return loss measurement. figure 51. minimum receiver eye timing and voltage compliance specification
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 freescale semiconductor 75 serial rapidio 14.5.1 compliance test and measurement load the ac timing and voltage parameters must be verified at the measurement point, as specified within 0.2 inches of the package pins, into a test/measurement load shown in figure 52 . note the allowance of the measurement point to be within 0.2 inches of the package pins is meant to acknowledge that package/board routing may benefit from d+ and d? not being exac tly matched in length at the package pin boundary. figure 52. compliance test/measurement load 15 serial rapidio this section describes the dc and ac electrical sp ecifications for the rapidio interface of the mpc8640, for the lp-serial physical layer. the electrical speci fications cover both single and multiple-lane links. two transmitter types (short run and long run) on a single receiver are specified for each of three baud rates, 1.25, 2.50, and 3.125 gbaud. two transmitter specifications allow for solutions ra nging from simple board-to-board interconnect to driving two connectors across a backplane. a single rece iver specification is given that will accept signals from both the short run and long run transmitter specifications. the short run transmitter specifications should be used mainly for chip-to-chip connections on either the same printed circuit board or across a single connector . this covers the case where connections are made to a mezzanine (daughter) card. the minimum swings of the short run specification reduce the overall power used by the transceivers. the long run transmitter specifications use larger voltage swings that are capable of driving signals across backplanes. this allows a user to drive signals acr oss two connectors and a backplane. the specifications allow a distance of at least 50 cm at all baud rates. all unit intervals are specified with a tolerance of 100 ppm. the worst case frequency difference between any transmit and receive clock will be 200 ppm.
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 76 freescale semiconductor serial rapidio to ensure interoperability between drivers and receivers of different vendors and technologies, ac coupling at the receiver input must be used. 15.1 dc requirements for serial rapidio sd n _ref_clk and sd n _ref_clk for more information, see section 13.2, ?serdes reference clocks.? 15.2 ac requirements for serial rapidio sd n _ref_clk and sd n _ref_clk table 51 lists ac requirements. 15.3 signal definitions lp-serial links use differential signaling. this se ction defines terms used in the description and specification of differential signals. figure 53 shows how the signals are defined. the figures show waveforms for either a transmitter output (td and td ) or a receiver input (rd and rd ). each signal swings between a volts and b volts where a > b. using these waveforms, the definitions are as follows: 1. the transmitter output signals and the receiver input signals td, td , rd and rd each have a peak-to-peak swing of a ? b volts 2. the differential output signal of the transmitter, v od , is defined as v td ?v td 3. the differential input signal of the receiver, v id , is defined as v rd ?v rd 4. the differential output signal of the transmitter and the differential input signal of the receiver each range from a ? b to ?(a ? b) volts table 51. sd n _ref_clk and sd n _ref_clk ac requirements symbol parameter description min typical max units comments t ref refclk cycle time ? 10(8) ? ns 8 ns applies only to serial rapidio with 125-mhz reference clock t refcj refclk cycle-to-cycle jitter. difference in the period of any two adjacent refclk cycles ? ? 80 ps ? t refpj phase jitter. deviation in edge location with respect to mean edge location ?40 ? 40 ps ?
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 freescale semiconductor 77 serial rapidio 5. the peak value of the differential transmitte r output signal and the differential receiver input signal is a ? b volts 6. the peak-to-peak value of the differential transmitter output signal and the differential receiver input signal is 2 (a ? b) volts figure 53. differential peak-peak voltage of transmitter or receiver to illustrate these definitions using real values, consider the case of a current mode logic (cml) transmitter that has a common mode voltage of 2.25 v and each of its outputs, td and td , has a swing that goes between 2.5 v and 2.0 v. using these values, the peak-to-peak voltage swing of the signals td and td is 500 mv p-p. the differential output signa l ranges between 500 mv and ?500 mv. the peak differential voltage is 500 mv. the peak-to-peak differential voltage is 1000 mv p-p. 15.4 equalization with the use of high speed serial links, the interconn ect media causes degradation of the signal at the receiver. effects such as inter-symbol interference (isi) or data-dependent jitter are produced. this loss can be large enough to degrade the eye opening at the r eceiver beyond what is allowed in the specification. to negate a portion of these effects, equalization can be used. the most common equalization techniques that can be used are: ? a passive high pass filter network placed at the receiver, often referred to as passive equalization. ? the use of active circuits in the receiver, often referred to as adaptive equalization. 15.5 explanatory note on transmitter and receiver specifications ac electrical specifications are given for transmitter and receiver. long run and short run interfaces at three baud rates (a total of six cases) are described. the parameters for the ac electrical specifications are guided by the xaui electrical interface specified in clause 47 of ieee 802.3ae-2002. xaui has similar application goals to the serial rapi dio interface. the goal of this standard is that electrical designs for the serial rapidio interface can reuse electrical designs for xaui, suitably modified for applications at the baud interv als and reaches described herein. differential peak-peak = 2 * (a-b) a volts td or rd td or rd b volts
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 78 freescale semiconductor serial rapidio 15.6 transmitter specifications lp-serial transmitter electrical and timing specifications are stated in the text and table 52 through table 57 . the differential return loss, s11, of the transmitter in each case shall be better than ? ?10 db for (baud frequency)/10 < freq(f) < 625 mhz ? ?10 db + 10log(f/625 mhz) db for 625 mhz freq(f) baud frequency the reference impedance for the differential return loss measurements is 100- resistive. differential return loss includes contributions from on-chip circuitry, chip packaging and any off-chip components related to the driver. the output impedance requirement applies to all valid output levels. it is recommended that the 20%?80% rise/fall time of the transmitter, as measured at the transmitter output, in each case have a minimum value 60 ps. it is recommended that the timing skew at the output of an lp-serial transmitter between the two signals that comprise a differential pair not exceed 25 ps at 1.25 gb, 20 ps at 2.50 gb and 15 ps at 3.125 gb. table 52. short run transmitter ac timing specifications?1.25 gbaud parameter symbol range unit notes min max output voltage v o ?0.40 2.30 volts voltage relative to common of either signal comprising a differential pair differential output voltage v diffpp 500 1000 mv p-p ? deterministic jitter j d ? 0.17 ui p-p ? total jitter j t ? 0.35 ui p-p ? multiple output skew s mo ? 1000 ps skew at the transmitter output between lanes of a multilane link unit interval ui 800 800 ps 100 ppm table 53. short run transmitter ac timing specifications?2.5 gbaud parameter symbol range unit notes min max output voltage v o ?0.40 2.30 volts voltage relative to common of either signal comprising a differential pair differential output voltage v diffpp 500 1000 mv p-p ? deterministic jitter j d ?0.17 ui p-p ? total jitter j t ?0.35 ui p-p ?
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 freescale semiconductor 79 serial rapidio tc: what was this? was there a figure here? multiple output skew s mo ? 1000 ps skew at the transmitter output between lanes of a multilane link unit interval ui 400 400 ps 100 ppm table 54. short run transmitter ac timing specifications?3.125 gbaud parameter symbol range unit notes min max output voltage, v o ?0.40 2.30 volts voltage relative to common of either signal comprising a differential pair differential output voltage v diffpp 500 1000 mv p-p ? deterministic jitter j d ?0.17 ui p-p ? total jitter j t ?0.35 ui p-p ? multiple output skew s mo ? 1000 ps skew at the transmitter output between lanes of a multilane link unit interval ui 320 320 ps 100 ppm table 55. long run transmitter ac timing specifications?1.25 gbaud parameter symbol range unit notes min max output voltage, v o ?0.40 2.30 volts voltage relative to common of either signal comprising a differential pair differential output voltage v diffpp 800 1600 mv p-p ? deterministic jitter j d ? 0.17 ui p-p ? total jitter j t ? 0.35 ui p-p ? multiple output skew s mo ? 1000 ps skew at the transmitter output between lanes of a multilane link unit interval ui 800 800 ps 100 ppm table 53. short run transmitter ac timing specifications?2.5 gbaud (continued) parameter symbol range unit notes min max
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 80 freescale semiconductor serial rapidio for each baud rate at which an lp-serial transmitter is specified to operate, the output eye pattern of the transmitter shall fall entirely within the unshaded portion of the transmitter output compliance mask shown in figure 54 . this figure should be used with the parameters specified in table 58 when measured at the output pins of the device and the device is driving a 100- 5% differential resistive load. the output eye pattern of an lp-serial transmitter that implements pre-emphasis (to equalize the link and reduce table 56. long run transmitter ac timing specifications?2.5 gbaud parameter symbol range unit notes min max output voltage, v o ?0.40 2.30 volts voltage relative to common of either signal comprising a differential pair differential output voltage v diffpp 800 1600 mv p-p ? deterministic jitter j d ?0.17 ui p-p ? total jitter j t ?0.35 ui p-p ? multiple output skew s mo ? 1000 ps skew at the transmitter output between lanes of a multilane link unit interval ui 400 400 ps 100 ppm table 57. long run transmitter ac timing specifications?3.125 gbaud parameter symbol range unit notes min max output voltage, v o ?0.40 2.30 volts voltage relative to common of either signal comprising a differential pair differential output voltage v diffpp 800 1600 mv p-p ? deterministic jitter j d ? 0.17 ui p-p ? total jitter j t ? 0.35 ui p-p ? multiple output skew s mo ? 1000 ps skew at the transmitter output between lanes of a multilane link unit interval ui 320 320 ps 100 ppm
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 freescale semiconductor 81 serial rapidio inter-symbol interference) need only comply with the transmitter output compliance mask when pre-emphasis is disabled or minimized. figure 54. transmitter output compliance mask table 58 specifies the parameters for the transmitter differential output eye diagram. 15.7 receiver specifications lp-serial receiver electrical and timing speci fications are stated in the text and table 59 through table 61 . receiver input impedance shall result in a differential return loss better that 10 db and a common mode return loss better than 6 db from 100 mhz to (0.8) (baud frequency). this in cludes contributions from on-chip circuitry, the chip package and any off-chip components related to the receiver. ac-coupling table 58. transmitter differential output eye diagram parameters tr a n sm it te r typ e v diff min (mv) v diff max (mv) a (ui) b (ui) 1.25 gbaud short range 250 500 0.175 0.39 1.25 gbaud long range 400 800 0.175 0.39 2.5 gbaud short range 250 500 0.175 0.39 2.5 gbaud long range 400 800 0.175 0.39 3.125 gbaud short range 250 500 0.175 0.39 3.125 gbaud long range 400 800 0.175 0.39 0 v diff min v diff max ?v diff min ? v diff max 0b1-b1 time in ui transmitter differential output voltage a1-a
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 82 freescale semiconductor serial rapidio components are included in this requirement. the refe rence impedance for return loss measurements is 100- resistive for differential return loss and 25- resistive for common mode. table 59. receiver ac timing specifications?1.25 gbaud parameter symbol range unit notes min max differential input voltage v in 200 1600 mv p-p measured at receiver deterministic jitter tolerance j d 0.37 ? ui p-p measured at receiver combined deterministic and random jitter tolerance j dr 0.55 ? ui p-p measured at receiver total jitter tolerance 1 j t 0.65 ? ui p-p measured at receiver multiple input skew s mi ? 24 ns skew at the receiver input between lanes of a multilane link bit error rate ber ? 10 ?12 ?? unit interval ui 800 800 ps +/? 100 ppm note: 1. total jitter is composed of three components, deterministic jitter, random jitter and single frequency sinusoidal jitter. th e sinusoidal jitter may have any amplitude and frequency in the unshaded region of figure 55 . the sinusoidal jitter component is included to ensure margin for low frequency jitter, wander, noise, crosstalk and other variable system effects. table 60. receiver ac timing specifications?2.5 gbaud parameter symbol range unit notes min max differential input voltage v in 200 1600 mv p-p measured at receiver deterministic jitter tolerance j d 0.37 ? ui p-p measured at receiver combined deterministic and random jitter tolerance j dr 0.55 ? ui p-p measured at receiver total jitter tolerance 1 j t 0.65 ? ui p-p measured at receiver multiple input skew s mi ? 24 ns skew at the receiver input between lanes of a multilane link bit error rate ber ? 10 ?12 ?? unit interval ui 400 400 ps 100 ppm note: 1. total jitter is composed of three components, deterministic jitter, random jitter and single frequency sinusoidal jitter. th e sinusoidal jitter may have any amplitude and frequency in the unshaded region of figure 55 . the sinusoidal jitter component is included to ensure margin for low frequency jitter, wander, noise, crosstalk and other variable system effects.
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 freescale semiconductor 83 serial rapidio table 61. receiver ac timing specifications?3.125 gbaud characteristic symbol range unit notes min max differential input voltage v in 200 1600 mv p-p measured at receiver deterministic jitter tolerance j d 0.37 ? ui p-p measured at receiver combined deterministic and random jitter tolerance j dr 0.55 ? ui p-p measured at receiver total jitter tolerance 1 j t 0.65 ? ui p-p measured at receiver multiple input skew s mi ? 22 ns skew at the receiver input between lanes of a multilane link bit error rate ber ? 10 -12 ?? unit interval ui 320 320 ps 100 ppm note: 1. total jitter is composed of three components, deterministic jitter, random jitter and single frequency sinusoidal jitter. th e sinusoidal jitter may have any amplitude and frequency in the unshaded region of figure 55 . the sinusoidal jitter component is included to ensure margin for low frequency jitter, wander, noise, crosstalk, and other variable system effects.
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 84 freescale semiconductor serial rapidio figure 55 shows the single frequency sinusoidal jitter limits. figure 55. single frequency sinusoidal jitter limits 8.5 ui p-p 0.10 ui p-p sinusoidal jitter amplitude 22.1 khz 1.875 mhz 20 mhz frequency
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 freescale semiconductor 85 serial rapidio 15.8 receiver eye diagrams for each baud rate at which an lp-serial receiver is specified to operate, the receiver shall meet the corresponding bit error rate specification ( table 59 through table 61 ) when the eye pattern of the receiver test signal (exclusive of sinusoidal jitter) falls entirely within the unshaded portion of the shown in figure 56 with the parameters specified in table 62 . the eye pattern of the receiver test signal is measured at the input pins of the receiving devi ce with the device replaced with a 100 5% differential resistive load. figure 56. receiver input compliance mask table 62 shows the parameters for the receiver input compliance mask exclusive of sinusoidal jitter. table 62. receiver input compliance mask parameters exclusive of sinusoidal jitter receiver type v diff min (mv) v diff max (mv) a (ui) b (ui) 1.25 gbaud 100 800 0.275 0.400 2.5 gbaud 100 800 0.275 0.400 3.125 gbaud 100 800 0.275 0.400 1 0 v diff max ?v diff max v diff min ?v diff min time (ui) receiver differential input voltage 0 ab 1-b1-a
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 86 freescale semiconductor serial rapidio 15.9 measurement and test requirements since the lp-serial electrical specification are guide d by the xaui electrical interface specified in clause 47 of ieee 802.3ae-2002, the measurement and test requirements defined here are similarly guided by clause 47. in addition, the cjpat test pattern defi ned in annex 48a of ieee802.3ae-2002 is specified as the test pattern for use in eye pattern and j itter measurements. annex 48b of ieee802.3ae-2002 is recommended as a reference for additiona l information on jitter test methods. 15.9.1 eye template measurements for the purpose of eye template measurements, the effects of a single-pole high pass filter with a 3 db point at (baud frequency) 1667 is applied to the jitter. the data pattern for template measurements is the continuous jitter test pattern (cjpat) defined in a nnex 48a of ieee802.3ae. all lanes of the lp-serial link shall be active in both the transmit and receive directions, and opposite ends of the links shall use asynchronous clocks. four lane imple mentations shall use cjpat as defined in annex 48a. single lane implementations shall use the cjpat sequence specifi ed in annex 48a for transmission on lane 0. the amount of data represented in the eye shall be adequate to ensure that the bit error ratio is less than 10 -12 . the eye pattern shall be measured with ac coupling and the compliance template centered at 0 v differential. the left and right edges of the template shall be aligned with the mean zero crossing points of the measured data eye. the load for this test shall be 100- resistive 5% differential to 2.5 ghz. 15.9.2 jitter test measurements for the purpose of jitter measurement, the effects of a si ngle-pole high pass filter with a 3 db point at (baud frequency) 1667 is applied to the jitter. the data pattern for jitter measurem ents is the continuous jitter test pattern (cjpat) pattern define d in annex 48a of ieee802.3ae. all lanes of the lp-serial link shall be active in both the transmit and receive directions , and opposite ends of the links shall use asynchronous clocks. four lane implementations shall use cjpat as defined in annex 48a. si ngle lane implementations shall use the cjpat sequence specified in annex 48a fo r transmission on lane 0. jitter shall be measured with ac coupling and at 0 v differential. jitter measurement for the transmitter (or for calibration of a jitter tolerance setup) shall be performed with a test pro cedure resulting in a ber curve such as that described in annex 48b of ieee802.3ae. 15.9.3 transmit jitter transmit jitter is measured at the driver output when terminated into a load of 100- resistive 5% differential to 2.5 ghz. 15.9.4 jitter tolerance jitter tolerance is measured at the receiver using a jitte r tolerance test signal. this signal is obtained by first producing the sum of deterministic and random jitter defined in section 15.7, ?receiver specifications,? and then adjusting the signal amplitude until the data eye contacts the six points of the minimum eye opening of the receive template shown in figure 56 and table 62 . note that for this to occur, the test signal must have vertical waveform symmetry about the av erage value and have horizontal symmetry (including jitter) about the mean zero crossing. eye templa te measurement requirements are as defined above.
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 freescale semiconductor 87 package random jitter is calibrated using a high pass filte r with a low frequency corner at 20 mhz and a 20 db/decade roll-off below this. the required sinusoidal jitter specified in section 15.7, ?receiver specifications,? is then added to the signal and the test load is replaced by the receiver being tested. 16 package this section details package parameters and dimensions. 16.1 package parameters for the mpc8640 the package parameters are as provided in the following list. the package type is 33 mm 33 mm, 1023 pins. there are two package options: high-lead flip chip-ceramic ball grid array (fc-cbga) and lead-free (fc-cbga). for all package types: die size 12.1 mm 14.7 mm package outline 33 mm 33 mm interconnects 1023 pitch 1 mm total capacitor count 43 caps; 100 nf each for high-lead fc-cbga (package option: hcte 1 hx) maximum module height 2.97 mm minimum module height 2.47 mm solder balls 89.5% pb 10.5% sn ball diameter (typical 2 ) 0.60 mm for rohs lead-free fc-cbga (package option: hcte 1 vu) maximum module height 2.77 mm minimum module height 2.27 mm solder balls 95.5% sn 4.0% ag 0.5% cu ball diameter (typical 2 ) 0.60 mm 1 high-coefficient of thermal expansion 2 typical ball diameter is before reflow
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 88 freescale semiconductor package 16.2 mechanical dimensions of the mpc8640 fc-cbga the mechanical dimensions and bottom surface nomenclature of the mpc8640d (dual core) and mpc8640 (single core) high-lead fc-cbga (packa ge option: hcte hx) and lead-free fc-cbga (package option: hcte vu) are shown respectfully in figure 57 and figure 58 . figure 57. mpc8640d high-lead fc-cbga dimensions
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 freescale semiconductor 89 package notes for figure 57 1. all dimensions are in millimeters. 2. dimensions and tolerances per asme y14.5m-1994. 3. maximum solder ball diameter measured parallel to datum a. 4. datum a, the seating plane, is defined by the spherical crowns of the solder balls. 5. capacitors may not be present on all devices. 6. caution must be taken not to short capacitors or expose metal capacitor pads on package top. 7. all dimensions symmetrical about centerlines unless otherwise specified. 8. note that for mpc8640 (single core) the solder balls for the following signals/pins are not populated in the package: vdd_core1 (r16, r18, r20, t17, t19, t21, t23, u16, u18, u22, v17, v19, v21, v23, w16, w18, w20, w22, y17, y19, y21, y23, aa16, aa18, aa20, aa22, ab23, ac24) and sensevdd_core1 (u20).
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 90 freescale semiconductor package figure 58. mpc8640d lead-free fc-cbga dimensions
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 freescale semiconductor 91 signal listings notes for figure 58 1. all dimensions are in millimeters. 2. dimensions and tolerances per asme y14.5m-1994. 3. maximum solder ball diameter measured parallel to datum a. 4. datum a, the seating plane, is defined by the spherical crowns of the solder balls. 5. capacitors may not be present on all devices. 6. caution must be taken not to short capacitors or expose metal capacitor pads on package top. 7. all dimensions symmetrical about centerlines unless otherwise specified. 8. note that for mpc8640 (single core) the solder balls for the following signals/pins are not populated in the package: vdd_core1 (r16, r18, r20, t17, t19, t21, t23, u16, u18, u22, v17, v19, v21, v23, w16, w18, w20, w22, y17, y19, y21, y23, aa16, aa18, aa20, aa22, ab23, ac24) and sensevdd_core1 (u20). 17 signal listings table 63 provides the pin assignments for the signals. notes for the signal changes on the single core device (mpc8640) are italicized and prefixed by s . table 63. mpc8640 signal reference by functional block name 1 package pin number pin type power supply notes ddr memory interface 1 signals 2,3 d1_mdq[0:63] d15, a14, b12, d12, a15, b15, b13, c13, c11, d11, d9, a8, a12, a11, a9, b9, f11, g12, k11, k12, e10, e9, j11, j10, g8, h10, l9, l7, f10, g9, k9, k8, ac6, ac7, ag8, ah9, ab6, ab8, ae9, af9, al8, am8, am10, ak11, ah8, ak8, aj10, ak10, al12, aj12, al14, am14, al11, am11, am13, ak14, am15, aj16, ak18, al18, aj15, al15, al17, am17 i/o d1_gv dd ? d1_mecc[0:7] m8, m7, r8, t10, l11, l10, p9, r10 i/o d1_gv dd ? d1_mdm[0:8] c14, a10, g11, h9, ad7, aj9, am12, ak16, n10 o d1_gv dd ? d1_mdqs[0:8] a13, c10, h12, j7, ae8, am9, ak13, ak17, n9 i/o d1_gv dd ? d1_mdqs [0:8] d14, b10, h13, j8, ad8, al9, aj13, am16, p10 i/o d1_gv dd ? d1_mba[0:2] aa8, aa10, t9 o d1_gv dd ? d1_ma[0:15] y10, w8, w9, v7, v8, u6, v10, u9, u7, u10, y9, t6, t8, ae12, r7, p6 o d1_gv dd ? d1_mwe ab11 o d1_gv dd ? d1_mras ab12 o d1_gv dd ? d1_mcas ac10 o d1_gv dd ? d1_mcs [0:3] ab9, ad10, ac12, ad11 o d1_gv dd ? d1_mcke[0:3] p7, m10, n8, m11 o d1_gv dd 23 d1_mck[0:5] w6, e13, ah11, y7, f14, ag10 o d1_gv dd ?
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 92 freescale semiconductor signal listings d1_mck [0:5] y6, e12, ah12, aa7, f13, ag11 o d1_gv dd ? d1_modt[0:3] ac9, af12, ae11, af10 o d1_gv dd ? d1_mdic[0:1] e15, g14 io d1_gv dd 27 d1_mv ref am18 ddr port 1 reference voltage d1_gv dd /2 3 ddr memory interface 2 signals 2,3 d2_mdq[0:63] a7, b7, c5, d5, c8, d8, d6, a5, c4, a3, d3, d2, a4, b4, c2, c1, e3, e1, h4, g1, d1, e4, g3, g2, j4, j2, l1, l3, h3, h1, k1, l4, aa4, aa2, ad1, ad2, y1, aa1, ac1, ac3, ad5, ae1, ag1, ag2, ac4, ad4, af3, af4, ah3, aj1, am1, am3, ah1, ah2, al2, al3, ak5, al5, ak7, am7, ak4, am4, am6, aj7 i/o d2_gv dd ? d2_mecc[0:7] h6, j5, m5, m4, g6, h7, m2, m1 i/o d2_gv dd ? d2_mdm[0:8] c7, b3, f4, j1, ab1, ae2, ak1, am5, k6 o d2_gv dd ? d2_mdqs[0:8] b6, b1, f1, k2, ab3, af1, al1, al6, l6 i/o d2_gv dd ? d2_mdqs [0:8] a6, a2, f2, k3, ab2, ae3, ak2, aj6, k5 i/o d2_gv dd ? d2_mba[0:2] w5, v5, p3 o d2_gv dd ? d2_ma[0:15] w1, u4, u3, t1, t2, t3, t5, r2, r1, r5, v4, r4, p1, ah5, p4, n1 o d2_gv dd ? d2_mwe y4 o d2_gv dd ? d2_mras w3 o d2_gv dd ? d2_mcas ab5 o d2_gv dd ? d2_mcs [0:3] y3, af6, aa5, af7 o d2_gv dd ? d2_mcke[0:3] n6, n5, n2, n3 o d2_gv dd 23 d2_mck[0:5] u1, f5, aj3, v2, e7, ag4 o d2_gv dd ? d2_mck [0:5] v1, g5, aj4, w2, e6, ag5 o d2_gv dd ? d2_modt[0:3] ae6, ag7, ae5, ah6 o d2_gv dd ? d2_mdic[0:1] f8, f7 io d2_gv dd 27 d2_mv ref a18 ddr port 2 reference voltage d2_gv dd /2 3 high speed i/o interface 1 (serdes 1) 4 sd1_tx[0:7] l26, m24, n26, p24, r26, t24, u26, v24 o sv dd ? sd1_tx [0:7] l27, m25, n27, p25, r27, t25, u27, v25 o sv dd ? sd1_rx[0:7] j32, k30, l32, m30, t30, u32, v30, w32 i sv dd ? table 63. mpc8640 signal reference by functional block (continued) name 1 package pin number pin type power supply notes
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 freescale semiconductor 93 signal listings sd1_rx [ 0:7] j31, k29, l31, m29, t29, u31, v29, w31 i sv dd ? sd1_ref_clk n32 i sv dd ? sd1_ref_clk n31 i sv dd ? sd1_imp_cal_tx y26 analog sv dd 19 sd1_imp_cal_rx j28 analog sv dd 30 sd1_pll_tpd u28 o sv dd 13, 17 sd1_pll_tpa t28 analog sv dd 13, 18 sd1_dll_tpd n28 o sv dd 13, 17 sd1_dll_tpa p31 analog sv dd 13, 18 high speed i/o interface 2 (serdes 2) 4 sd2_tx[0:3] y24, aa27, ab25, ac27 o sv dd ? sd2_tx[4:7] ae27, ag27, aj27, al27 o sv dd 34 sd2_tx [0:3] y25, aa28, ab26, ac28 o sv dd ? sd2_tx [4:7] ae28, ag28, aj28, al28 o sv dd 34 sd2_rx[0:3] y30, aa32, ab30, ac32 i sv dd 32 sd2_rx[4:7] ah30, aj32, ak30, al32 i sv dd 32, 35 sd2_rx [ 0:3] y29, aa31, ab29, ac31 i sv dd ? sd2_rx [ 4:7] ah29, aj31, ak29, al31 i sv dd 35 sd2_ref_clk ae32 i sv dd ? sd2_ref_clk ae31 i sv dd ? sd2_imp_cal_tx am29 analog sv dd 19 sd2_imp_cal_rx aa26 analog sv dd 30 sd2_pll_tpd af29 o sv dd 13, 17 sd2_pll_tpa af31 analog sv dd 13, 18 sd2_dll_tpd ad29 o sv dd 13, 17 sd2_dll_tpa ad30 analog sv dd 13, 18 special connection requirement pins no connects k24, k25, p28, p29, w26, w27, ad25, ad26 ?? 13 reserved h30, r32, v28, ag32 ? ? 14 reserved h29, r31, w28, ag31 ? ? 15 reserved ad24, ag26 ? ? 16 ethernet miscellaneous signals 5 table 63. mpc8640 signal reference by functional block (continued) name 1 package pin number pin type power supply notes
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 94 freescale semiconductor signal listings ec1_gtx_clk125 al23 i lv dd 39 ec2_gtx_clk125 am23 i tv dd 39 ec_mdc g31 o ov dd ? ec_mdio g32 i/o ov dd ? etsec port 1 signals 5 tsec1_txd[0:7]/ gpout[0:7] af25, ac23,ag24, ag23, ae24, ae23, ae22, ad22 olv dd 6, 10 tsec1_tx_en ab22 o lv dd 36 tsec1_tx_er ah26 o lv dd ? tsec1_tx_clk ac22 i lv dd 40 tsec1_gtx_clk ah25 o lv dd 41 tsec1_crs am24 i/o lv dd 37 tsec1_col am25 i lv dd ? tsec1_rxd[0:7]/ gpin[0:7] al25, al24, ak26, ak25, am26, af26, ah24, ag25 ilv dd 10 tsec1_rx_dv aj24 i lv dd ? tsec1_rx_er aj25 i lv dd ? tsec1_rx_clk ak24 i lv dd 40 etsec port 2 signals 5 tsec2_txd[0:3]/ gpout[8:15] ab20, aj23, aj22, ad19 o lv dd 6, 10 tsec2_txd[4]/ gpout[12] ah23 o lv dd 6,10, 38 tsec2_txd[5:7]/ gpout[13:15] ah21, ag22, ag21 o lv dd 6, 10 tsec2_tx_en ab21 o lv dd 36 tsec2_tx_er ab19 o lv dd 6, 38 tsec2_tx_clk ac21 i lv dd 40 tsec2_gtx_clk ad20 o lv dd 41 tsec2_crs ae20 i/o lv dd 37 tsec2_col ae21 i lv dd ? tsec2_rxd[0:7]/ gpin[8:15] al22, ak22, am21, ah20, ag20, af20, af23, af22 ilv dd 10 tsec2_rx_dv ac19 i lv dd ? tsec2_rx_er ad21 i lv dd ? table 63. mpc8640 signal reference by functional block (continued) name 1 package pin number pin type power supply notes
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 freescale semiconductor 95 signal listings tsec2_rx_clk am22 i lv dd 40 etsec port 3 signals 5 tsec3_txd[0:3] al21, aj21, am20, aj20 o tv dd 6 tsec3_txd[4]/ am19 o tv dd ? tsec3_txd[5:7] ak21, al20, al19 o tv dd 6 tsec3_tx_en ah19 o tv dd 36 tsec3_tx_er ah17 o tv dd ? tsec3_tx_clk ah18 i tv dd 40 tsec3_gtx_clk ag19 o tv dd 41 tsec3_crs ae15 i/o tv dd 37 tsec3_col af15 i tv dd ? tsec3_rxd[0:7] aj17, ae16, ah16, ah14, aj19, ah15, ag16, ae19 itv dd ? tsec3_rx_dv ag15 i tv dd ? tsec3_rx_er af16 i tv dd ? tsec3_rx_clk aj18 i tv dd 40 etsec port 4 signals 5 tsec4_txd[0:3] ac18, ac16, ad18, ad17 o tv dd 6 tsec4_txd[4] ad16 o tv dd 25 tsec4_txd[5:7] ab18, ab17, ab16 o tv dd 6 tsec4_tx_en af17 o tv dd 36 tsec4_tx_er af19 o tv dd ? tsec4_tx_clk af18 i tv dd 40 tsec4_gtx_clk ag17 o tv dd 41 tsec4_crs ab14 i/o tv dd 37 tsec4_col ac13 i tv dd ? tsec4_rxd[0:7] ag14, ad13, af13, ad14, ae14, ab15, ac14, ae17 itv dd ? tsec4_rx_dv ac15 i tv dd ? tsec4_rx_er af14 i tv dd ? tsec4_rx_clk ag13 i tv dd 40 table 63. mpc8640 signal reference by functional block (continued) name 1 package pin number pin type power supply notes
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 96 freescale semiconductor signal listings local bus signals 5 lad[0:31] a30, e29, c29, d28, d29, h25, b29, a29, c28, l22, m22, a28, c27, h26, g26, b27, b26, a27, e27, g25, d26, e26, g24, f27, a26, a25, c25, h23, k22, d25, f25, h22 i/o ov dd 6 ldp[0:3] a24, e24, c24, b24 i/o ov dd 6, 22 la[27:31] j21, k21, g22, f24, g21 o ov dd 6, 22 lcs [0:4] a22, c22, d23, e22, a23 o ov dd 7 lcs [5]/dma_dreq [2] b23 o ov dd 7, 9, 10 lcs [6]/dma_dack[ 2] e23 o ov dd 7, 10 lcs [7]/dma_ddone [2] f23 o ov dd 7, 10 lwe [0:3]/ lsddqm[0:3]/ lbs [0:3] e21, f21, d22, e20 o ov dd 6 lbctl d21 o ov dd ? lale e19 o ov dd ? lgpl0/lsda10 f20 o ov dd 25 lgpl1/lsdwe h20 o ov dd 25 lgpl2/loe / lsdras j20 o ov dd ? lgpl3/lsdcas k20 o ov dd 6 lgpl4/lgta / lupwait/lpbse l21 i/o ov dd 42 lgpl5 j19 o ov dd 6 lcke h19 o ov dd ? lclk[0:2] g19, l19, m20 o ov dd ? lsync_in m19 i ov dd ? lsync_out d20 o ov dd ? dma signals 5 dma_dreq [0:1] e31, e32 i ov dd ? dma_dreq [2]/lcs [5] b23 i ov dd 9, 10 dma_dreq [3]/irq[9] b30 i ov dd 10 dma_dack [0:1] d32, f30 o ov dd ? dma_dack[2] /lcs [6] e23 o ov dd 10 dma_dack[3 ]/irq[10] c30 o ov dd 9, 10 table 63. mpc8640 signal reference by functional block (continued) name 1 package pin number pin type power supply notes
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 freescale semiconductor 97 signal listings dma_ddone [0:1] f31, f32 o ov dd ? dma_ddone [2]/lcs[7] f23 o ov dd 10 dma_ddone [3]/irq[11] d30 o ov dd 9, 10 programmable interrupt controller signals 5 mcp_0 f17 i ov dd ? mcp _1 h17 i ov dd 12, s4 irq[0:8] g28, g29, h27, j23, m23, j27, f28, j24, l23 iov dd ? irq[9]/dma_dreq[3] b30 i ov dd 10 irq[10]/dma_dack[3] c30 i ov dd 9, 10 irq[11]/dma_ddone[3] d30 i ov dd 9, 10 irq_out j26 o ov dd 7, 11 duart signals 5 uart_sin[0:1] b32, c32 i ov dd ? uart_sout[0:1] d31, a32 o ov dd ? uart_cts [0:1] a31, b31 i ov dd ? uart_rts [0:1] c31, e30 o ov dd ? i 2 c signals iic1_sda a16 i/o ov dd 7, 11 iic1_scl b17 i/o ov dd 7, 11 iic2_sda a21 i/o ov dd 7, 11 iic2_scl b21 i/o ov dd 7, 11 system control signals 5 hreset b18 i ov dd ? hreset_req k18 o ov dd ? smi_0 l15 i ov dd ? smi_1 l16 i ov dd 12, s4 sreset_0 c20 i ov dd ? sreset_1 c21 i ov dd 12, s4 ckstp_in l18 i ov dd ? ckstp_out l17 o ov dd 7, 11 ready/trig_out j13 o ov dd 10, 25 table 63. mpc8640 signal reference by functional block (continued) name 1 package pin number pin type power supply notes
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 98 freescale semiconductor signal listings debug signals 5 trig_in j14 i ov dd ? trig_out/ready j13 o ov dd 10, 25 d1_msrcid[0:1]/lb_sr cid[0:1] f15, k15 o ov dd 6, 10 d1_msrcid[2]/lb_srci d[2] k14 o ov dd 10, 25 d1_msrcid[3:4]/lb_sr cid[3:4] h15, g15 o ov dd 10 d2_msrcid[0:4] e16, c17, f16, h16, k16 o ov dd ? d1_mdval/lb_dval j16 o ov dd 10 d2_mdval d19 o ov dd ? power management signals 5 asleep c19 o ov dd ? system clocking signals 5 sysclk g16 i ov dd ? rtc k17 i ov dd 32 clk_out b16 o ov dd 23 test signals 5 lssd_mode c18 i ov dd 26 test_mode[0:3] c16, e17, d18, d16 i ov dd 26 jtag signals 5 tck h18 i ov dd ? tdi j18 i ov dd 24 tdo g18 o ov dd 23 tms f18 i ov dd 24 trst a17 i ov dd 24 miscellaneous 5 spare j17 ? ? 13 gpout[0:7]/ tsec1_txd[0:7] af25, ac23, ag24, ag23, ae24, ae23, ae22, ad22 oov dd 6, 10 gpin[0:7]/ tsec1_rxd[0:7] al25, al24, ak26, ak25, am26, af26, ah24, ag25 iov dd 10 gpout[8:15]/ tsec2_txd[0:7] ab20, aj23, aj22, ad19, ah23, ah21, ag22, ag21 oov dd 10 table 63. mpc8640 signal reference by functional block (continued) name 1 package pin number pin type power supply notes
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 freescale semiconductor 99 signal listings gpin[8:15]/ tsec2_rxd[0:7] al22, ak22, am21, ah20, ag20, af20, af23, af22 iov dd 10 additional analog signals temp_anode aa11 thermal ? ? temp_cathode y11 thermal ? ? sense, power and gnd signals sensev dd _core0 m14 v dd _core0 sensing pin ?31 sensev dd _core1 u20 v dd _core1 sensing pin ? 12,31, s1 sensev ss _core0 p14 core0 gnd sensing pin ?31 sensev ss _core1 v20 core1 gnd sensing pin ? 12, 31, s3 sensev dd _plat n18 v dd _plat sensing pin ?28 sensev ss _plat p18 platform gnd sensing pin ?29 d1_gv dd b11, b14, d10, d13, f9, f12, h8, h11, h14, k10, k13, l8, p8, r6, u8, v6, w10, y8, aa6, ab10, ac8, ad12, ae10, af8, ag12, ah10, aj8, aj14, ak12, al10, al16 sdram 1 i/o supply d1_gv dd ? 2.5 ddr ? 1.8 ddr2 ? d2_gv dd b2, b5, b8, d4, d7, e2, f6, g4, h2, j6, k4, l2, m6, n4, p2, t4, u2, w4, y2, ab4, ac2, ad6, ae4, af2, ag6, ah4, aj2, ak6, al4, am2 sdram 2 i/o supply d2_gv dd ? 2.5 v ddr ? 1.8 v ddr2 ? ov dd b22, b25, b28, d17, d24, d27, f19, f22, f26, f29, g17, h21, h24, k19, k23, m21, am30 duart, local bus, dma, multiprocessor interrupts, system control & clocking, debug, test, jtag, power management, i 2 c, jtag and miscellaneous i/o voltage ov dd 3.3 v ? lv dd ac20, ad23, ah22 tsec1 and tsec2 i/o voltage lv dd 2.5/3.3 v ? tv dd ac17, ag18, ak20 tsec3 and tsec4 i/o voltage tv dd 2.5/3.3 v ? table 63. mpc8640 signal reference by functional block (continued) name 1 package pin number pin type power supply notes
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 100 freescale semiconductor signal listings sv dd h31, j29, k28, k32, l30, m28, m31, n29, r30, t31, u29, v32, w30, y31, aa29, ab32, ac30, ad31, ae29, ag30, ah31, aj29, ak32, al30, am31 transceiver power supply serdes sv dd 1.05/1.1 v ? xv dd_ srds1 k26, l24, m27, n25, p26, r24, r28, t27, u25, v26 serial i/o power supply for serdes port 1 xv dd_ srds1 1.05/1.1 v xv dd_ srds2 aa25, ab28, ac26, ad27, ae25, af28, ah27, ak28, am27, w24, y27 serial i/o power supply for serdes port 2 xv dd_ srds2 1.05/1.1 v ? v dd _core0 l12, l13, l14, m13, m15, n12, n14, p11, p13, p15, r12, r14, t11, t13, t15, u12, u14, v11, v13, v15, w12, w14, y12, y13, y15, aa12, aa14, ab13 core 0 voltage supply v dd _core0 0.95/1.05/1.1 v ? v dd _core1 r16, r18, r20, t17, t19, t21, t23, u16, u18, u22, v17, v19, v21, v23, w16, w18, w20, w22, y17, y19, y21, y23, aa16, aa18, aa20, aa22, ab23, ac24 core 1 voltage supply v dd _core1 0.95/1.05/1.1 v 12, s1 v dd _plat m16, m17, m18, n16, n20, n22, p17, p19, p21, p23, r22 platform supply voltage v dd _plat 1.05/1.1 v ? av dd _core0 b20 core 0 pll supply av dd _core0 0.95/1.05/ 1.1 v ? av dd _core1 a19 core 1 pll supply av dd _core1 0.95/1.05/ 1.1 v 12, s2 av dd _plat b19 platform pll supply voltage av dd _plat 1.05/1.1 v ? av dd _lb a20 local bus pll supply voltage av dd _lb 1.05/1.1 v ? av dd _srds1 p32 serdes port 1 pll & dll power supply av dd _srds1 1.05/1.1 v ? av dd _srds2 af32 serdes port 2 pll & dll power supply av dd _srds2 1.05/1.1 v ? table 63. mpc8640 signal reference by functional block (continued) name 1 package pin number pin type power supply notes
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 freescale semiconductor 101 signal listings gnd c3, c6, c9, c12, c15, c23, c26, e5, e8, e11, e14, e18, e25, e28, f3, g7, g10, g13, g20, g23, g27, g30, h5, j3, j9, j12, j15, j22, j25, k7, l5, l20, m3, m9, m12, n7, n11, n13, n15, n17, n19, n21, n23, p5, p12, p16, p20, p22, r3, r9, r11, r13, r15, r17, r19, r21, r23, t7, t12, t14, t16, t18, t20, t22, u5, u11,u13, u15, u17, u19, u21, u23, v3, v9, v12, v14, v16, v18, v22, w7, w11, w13, w15, w17, w19, w21, w23,y5, y14, y16, y18, y20, y22, aa3, aa9, aa13, aa15, aa17, aa19, aa21, aa23, ab7, ab24, ac5, ac11, ad3, ad9, ad15, ae7, ae13, ae18, af5, af11, af21, af24, ag3, ag9, ah7, ah13, aj5, aj11, ak3, ak9, ak15, ak19, ak23, al7, al13 gnd ? ? agnd_srds1 p30 serdes port 1 ground pin for av dd _srds1 ?? agnd_srds2 af30 serdes port 2 ground pin for av dd _srds2 ?? sgnd h28, h32, j30, k31, l28, l29, m32, n30, r29, t32, u30, v31, w29,y32 aa30, ab31, ac29, ad32, ae30, ag29, ah32, aj30, ak31, al29, am32 ground pins for sv dd ?? xgnd k27, l25, m26, n24, p27, r25, t26, u24, v27, w25, y28, aa24, ab27, ac25, ad28, ae26, af27, ah28, aj26, ak27, al26, am28 ground pins for xv dd _srds n ?? reset configuration signals 20 tsec1_txd[0] / cfg_alt_boot_vec af25 ? lv dd ? tsec1_txd[1]/ cfg_platform_freq ac23 ? lv dd 21 tsec1_txd[2:4]/ cfg_device_id[5:7] ag24, ag23, ae24 ? lv dd ? tsec1_txd[5]/ cfg_tsec1_reduce ae23 ? lv dd ? tsec1_txd[6:7]/ cfg_tsec1_prtcl[0:1] ae22, ad22 ? lv dd ? tsec2_txd[0:3]/ cfg_rom_loc[0:3] ab20, aj23, aj22, ad19 ? lv dd ? tsec2_txd[4], tsec2_tx_er/ cfg_dram_type[0:1] ah23, ab19 ?lv dd 38 table 63. mpc8640 signal reference by functional block (continued) name 1 package pin number pin type power supply notes
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 102 freescale semiconductor signal listings tsec2_txd[5]/ cfg_tsec2_reduce ah21 ? lv dd ? tsec2_txd[6:7]/ cfg_tsec2_prtcl[0:1] ag22, ag21 ? lv dd ? tsec3_txd[0:1]/ cfg_spare[0:1] al21, aj21 o tv dd 33 tsec3_txd[2]/ cfg_core1_enable am20 o tv dd ? tsec3_txd[3]/ cfg_core1_lm_offset aj20 ? lv dd ? tsec3_txd[5]/ cfg_tsec3_reduce ak21 ? lv dd ? tsec3_txd[6:7]/ cfg_tsec3_prtcl[0:1] al20, al19 ? lv dd ? tsec4_txd[0:3]/ cfg_io_ports[0:3] ac18, ac16, ad18, ad17 ? lv dd ? tsec4_txd[5]/ cfg_tsec4_reduce ab18 ? lv dd ? tsec4_txd[6:7]/ cfg_tsec4_prtcl[0:1] ab17, ab16 ? lv dd ? lad[0:31]/ cfg_gpporcr[0:31] a30, e29, c29, d28, d29, h25, b29, a29, c28, l22, m22, a28, c27, h26, g26, b27, b26, a27, e27, g25, d26, e26, g24, f27, a26, a25, c25, h23, k22, d25, f25, h22 ?ov dd ? lwe[0] / cfg_cpu_boot e21 ? ov dd ? lwe[1] / cfg_rio_sys_size f21 ? ov dd ? lwe[2:3] / cfg_host_agt[0:1] d22, e20 ? ov dd ? ldp[0:3], la[27] / cfg_core_pll[0:4] a24, e24, c24, b24, j21 ?ov dd 22 la[28:31]/ cfg_sys_pll[0:3] k21, g22, f24, g21 ? ov dd 22 lgpl[3], lgpl[5]/ cfg_boot_seq[0:1] k20, j19 ?ov dd ? d1_msrcid[0]/ cfg_mem_debug f15 ? ov dd ? d1_msrcid[1]/ cfg_ddr_debug k15 ? ov dd ? table 63. mpc8640 signal reference by functional block (continued) name 1 package pin number pin type power supply notes
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 freescale semiconductor 103 signal listings note: 1. multi-pin signals such as d1_mdq[0:63] and d2_mdq[0:63] have their physical package pin numbers listed in order corresponding to the signal names. 2. stub series terminated logic (sstl-18 and sstl-25) type pins. 3. if a ddr port is not used, it is possible to leave the related power supply (dn_gvdd, dn_mvref) turned off at reset. note that these power supplies can only be powered up again at reset for functionality to occur on the ddr port. 4. low voltage differential signaling (lvds) type pins. 5. low voltage transistor-transistor logic (lvttl) type pins. 6. this pin is a reset configuration pin and appears again in the reset configuration signals section of this table. see the re set configuration signals section of this table for config name and connection details. 7. recommend a weak pull-up resistor (1?10 k ) be placed from this pin to its power supply. 8. recommend a weak pull-down resistor (2?10 k ) be placed from this pin to ground. 9. this multiplexed pin has input status in one mode and output in another 10. this pin is a multiplexed signal for different functional blocks and appears more than once in this table. 11. this pin is open drain signal. 12. functional only on the mpc8640d. 13. these pins should be left floating. 14. these pins should be connected to sv dd . 15. these pins should be pulled to ground with a strong resistor (270- to 330- ). 16. these pins should be connected to ovdd. 17.this is a serdes pll/dll digital test signal and is only for factory use. 18. this is a serdes pll/dll analog test signal and is only for factory use. 19. this pin should be pulled to ground with a 100- resistor. 20. the pins in this section are reset configuration pins. each pin has a weak internal pull-up p-fet which is enabled only whe n the processor is in the reset state. this pull-up is designed such that it can be overpowered by an external 4.7-k pull-down resistor. however, if the signal is intended to be high after reset, and if there is any device on the net which might pull dow n the value of the net at reset, then a pullup or active driver is needed. 21. should be pulled down at reset if platform frequency is at 400 mhz. 22. these pins require 4.7-k pull-up or pull-down resistors and must be driven as they are used to determine pll configuration ratios at reset. 23. this output is actively driven during reset rather than being released to high impedance during reset. 24 these jtag pins have weak internal pull-up p-fets that are always enabled. 25. this pin should not be pulled down (or driven low) during reset. 26.these are test signals for factory use only and must be pulled up (100- to 1- k .) to ovdd for normal machine operation. 27. dn_mdic[0] should be connected to ground with an 18- resistor 1- and dn_mdic[1] should be clonnected dn_gvdd with an 18- resistor 1- . these pins are used for automatic calibration of the ddr ios. 28. pin n18 is recommended as a reference point for determining the voltage of v dd _plat and is hence considered as the v dd _plat sensing voltage and is called sensevdd_plat. 29. pin p18 is recommended as the ground reference point for sensevdd_plat and is called sensevss_plat. 30.this pin should be pulled to ground with a 200- resistor. 31.these pins are connected to the power/ground planes internally and may be used by the core power supply to improve tracking and regulation. 32. must be tied low if unused 33. these pins may be used as defined functional reset configuration pins in the future. please include a resistor pull-up/down option to allow flexibility of future designs. 34. used as serial data output for serial rapidio 1 /4 link. 35. used as serial data input for serial rapidio 1 /4 link. 36.this pin requires an external 4.7-k pull-down resistor to prevent phy from seeing a valid transmit enable before it is actively driven. table 63. mpc8640 signal reference by functional block (continued) name 1 package pin number pin type power supply notes
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 104 freescale semiconductor clocking 18 clocking this section describes the pll configuration of the mpc8640. note that the platform clock is identical to the mpx clock. 18.1 clock ranges table 64 provides the clocking specifications for the processor cores, and table 65 provides the clocking specifications for the memory bus. table 66 provides the clocking for the platform/mpx bus, and table 67 provides the clocking for the local bus. 37.this pin is only an output in fifo mode when used as rx flow control. 38.this pin functions as cfg_dram_type[0 or 1] at reset. note: this pin must be valid before hreset assertion in device sleep mode. 39. should be pulled to ground if unused (such as in fifo, mii and rmii modes). 40. see section 18.4.2, ?platform to fifo restrictions ? for clock speed limitations for this pin when used in fifo mode. 41. the phase between the output clocks tsec1_gtx_clk and tsec2_gtx_clk (ports 1 and 2) is no more than 100 ps. the phase between the output clocks tsec3_gtx_clk and tsec4_gtx_clk (ports 3 and 4) is no more than 100 ps. 42. for systems which boot from local bus (gpcm)-controlled flash, a pullup on lgpl4 is required. special notes for single core device: s1 . solder ball for this signal will not be populated in the single core package. s2 . the pll filter from v dd _core1 to av dd _core1 should be removed. av dd _core1 should be pulled to ground with a weak (2?10 k ) resistor. see section 20.2.1, ?pll power supply filtering ? for more details. s3 . this pin should be pulled to gnd for the single core device. s4 . no special requirement for this pin on single core device. pin should be tied to power supply as directed for dual core. table 64. processor core clocking specifications parameter maximum processor core frequency unit notes 1000 mhz 1067 mhz 1250mhz min max min max min max e600 core processor frequency 800 1000 800 1067 800 1250 mhz 1, 2 notes : 1. caution: the mpx clock to sysclk ratio and e600 core to mpx clock ratio settings must be chosen such that the resulting sysclk frequency, e600 (core) frequency, and mpx clock frequency do not exceed their respective maximum or minimum operating frequencies. refer to section 18.2, ?mpx to sysclk pll ratio,? and section 18.3, ?e600 to mpx clock pll ratio,? for ratio settings. 2. the minimum e600 core frequency is based on the minimum platform clock frequency of 400 mhz. table 63. mpc8640 signal reference by functional block (continued) name 1 package pin number pin type power supply notes
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 freescale semiconductor 105 clocking 18.2 mpx to sysclk pll ratio the mpx clock is the clock that drives the mpx bus, a nd is also called the platform clock. the frequency of the mpx is set using the following reset signals, as shown in table 68 : ? sysclk input signal table 65. memory bus clocking specifications parameter maximum processor core frequency unit notes 1000, 1067, 1250 mhz min max memory bus clock frequency 200 266 mhz 1, 2 notes: 1. caution: the mpx clock to sysclk ratio and e600 core to mpx clock ratio settings must be chosen such that the resulting sysclk frequency, e600 (core) frequency, and mpx clock frequency do not exceed their respective maximum or minimum operating frequencies. refer to section 18.2, ?mpx to sysclk pll ratio,? and section 18.3, ?e600 to mpx clock pll ratio,? for ratio settings. 2. the memory bus clock speed is half the ddr/ddr2 data rate, hence, half the mpx clock frequency. table 66. platform/mpx bus clocking specifications parameter maximum processor core frequency unit notes 1000, 1067, 1250 mhz min max platform/mpx bus clock frequency 400 533 mhz 1, 2 notes: 1. caution: the mpx clock to sysclk ratio and e600 core to mpx clock ratio settings must be chosen such that the resulting sysclk frequency, e600 (core) frequency, and mpx clock frequency do not exceed their respective maximum or minimum operating frequencies. refer to section 18.2, ?mpx to sysclk pll ratio,? and section 18.3, ?e600 to mpx clock pll ratio,? for ratio settings. 2. platform/mpx frequencies between 400 and 500 mhz are not supported. table 67. local bus clocking specifications parameter maximum processor core frequency unit notes 1000, 1067, 1250 mhz min max local bus clock speed (for local bus controller) 25 133 mhz 1 notes: 1. the local bus clock speed on lclk[0:2] is determined by mpx clock divided by the local bus pll ratio programmed in lcrr[clkdiv]. see the reference manual for the mpc8641d for more information on this.
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 106 freescale semiconductor clocking ? binary value on la[28:31] at power up note that there is no default for this pll ratio; these signals must be pulled to the desired values. also note that the ddr data rate is the determining factor in selecting the mpx bus frequency because the mpx frequency must equal the ddr data rate. 18.3 e600 to mpx clock pll ratio table 69 describes the clock ratio between the platform a nd the e600 core clock. this ratio is determined by the binary value of ldp[0:3], la[27](cfg_core_pll[0: 4] - reset config name) at power up, as shown in table 69 . 18.4 frequency options this section discusses the frequency options for the mpc8640. table 68. mpx:sysclk ratio binary value of la[28:31] signals mpx:sysclk ratio 0000 reserved 0001 reserved 0010 2:1 0011 3:1 0100 4:1 0101 5:1 0110 6:1 0111 reserved 1000 8:1 1001 reserved table 69. e600 core to mpx clock ratio binary value of ldp[0:3], la[27] signals e600 core: mpx clock ratio 01000 2:1 01100 2.5:1 10000 3:1 11100 reserved 10100 reserved 01110 reserved
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 freescale semiconductor 107 thermal 18.4.1 sysclk to platform frequency options table 70 shows some sysclk frequencies and the e xpected mpx frequency values based on the mpx clock to sysclk ratio. note th at frequencies between 400 mhz and 500 mhz are not supported on the platform. see note regarding cfg_platform_freq in section 17, ?signal listings,? because it is a reset configuration pin that is rela ted to platform frequency. 18.4.2 platform to fifo restrictions please note the following fifo maximum speed restrictions based on platform speed: for fifo gmii mode: fifo tx/rx clock frequency platform clock frequency 4.2 for example, if the platform frequency is 500 mh z, the fifo tx/rx clock frequency should be no more than 119 mhz. for fifo encoded mode: fifo tx/rx clock frequency platform clock frequency 3.2 for example, if the platform frequency is 500 mh z, the fifo tx/rx clock frequency should be no more than 156 mhz. 19 thermal this section describes the thermal specifications of the mpc8640. table 70. frequency options of sysclk with respect to platform/mpx clock speed mpx to sysclk ratio sysclk (mhz) 66 83 100 133 167 platform/mpx frequency (mhz) 1 1 sysclk frequency range is 66-167 mhz. platform clock/mpx frequency range is 400 mhz, 500-533 mhz. 2 3 400 500 4 400 533 5 500 6 400 500 8 533
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 108 freescale semiconductor thermal 19.1 thermal characteristics table 71 provides the package thermal characteristics for the mpc8640. 19.2 thermal management information this section provides thermal mana gement information for the high co efficient of thermal expansion (hcte) package for air-cooled applications. proper th ermal control design is pr imarily dependent on the system-level design?the heat sink, airflow, and thermal interface materi al. the mpc8640 implements several features designed to assist with therma l management, including the temperature diode. the temperature diode allows an external device to monitor the die temperature in order to detect excessive temperature conditions and alert the system; see section 19.2.4, ?temperature diode,? for more information. to reduce the die-junction temperature, heat sinks are required. due to the potential large mass of the heat sink, attachment through the printed-circuit board is suggested. in any implementation of a heat sink solution, the force on the die should not exceed ten pounds force (45 newtons). figure 59 shows a spring table 71. package thermal characteristics 1 characteristic symbol value unit notes junction-to-ambient thermal resistance, natural convection, single-layer (1s) board r ja 18 c/w 1, 2 junction-to-ambient thermal resistance, natural convection, four-layer (2s2p) board r ja 13 c/w 1, 3 junction-to-ambient thermal resistance, 200 ft/min airflow, single-layer (1s) board r jma 13 c/w 1, 3 junction-to-ambient thermal resistance, 200 ft/min airflow, four-layer (2s2p) board r jma 9c/w1, 3 junction-to-board thermal resistance r jb 5c/w4 junction-to-case thermal resistance r jc < 0.1 c/w 5 notes : 1. junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2. per jedec jesd51-2 with the single-layer board (jesd51-3) horizontal. 3. per jedec jesd51-6 with the board (jesd51-7) horizontal. 4. thermal resistance between the die and the printed-circuit board per jedec jesd51-8. board temperature is measured on the top surface of the board near the package. 5. this is the thermal resistance between die and case top surface as measured by the cold plate method (mil spec-883 method 1012.1) with the calculated case temperature. actual thermal resistance is less than 0.1 c/w.
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 freescale semiconductor 109 thermal clip through the board. occasionally the spring clip is attached to soldered hooks or to a plastic backing structure. screw and spring arrangements are also frequently used. figure 59. fc-cbga package exploded cross-sectional view with several heat sink options there are several commercially-available heat si nks for the mpc8640 provided by the following vendors: aavid thermalloy 603-224-9988 80 commercial st. concord, nh 03301 internet: www.aavidthermalloy.com advanced thermal solutions 781-769-2800 89 access road #27. norwood, ma02062 internet: www.qats.com alpha novatech 408-749-7601 473 sapena ct. #12 santa clara, ca 95054 internet: www.alphanovatech.com calgreg thermal solutions 888-732-6100 60 alhambra road, suite 1 warwick, ri 02886 internet: www.calgreg.com international electronic research corporation (ierc)818-842-7277 413 north moss st. burbank, ca 91502 internet: www.ctscorp.com thermal heat sink hcte fc-cbga package heat sink clip printed-circuit board interface material
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 110 freescale semiconductor thermal millennium electronics (mei) 408-436-8770 loroco sites 671 east brokaw road san jose, ca 95112 internet: www.mei-thermal.com tyco electronics 800-522-6752 chip coolers? p.o. box 3668 harrisburg, pa 17105-3668 internet: www.chipcoolers.com wakefield engineering 603-635-5102 33 bridge st. pelham, nh 03076 internet: www.wakefield.com ultimately, the final selection of an appropriate heat sink depends on many factors, such as thermal performance at a given air veloc ity, spatial volume, mass, attachme nt method, assembly, and cost. 19.2.1 internal package conduction resistance for the exposed-die packaging technology described in table 71 , the intrinsic conduction thermal resistance paths are as follows: ? the die junction-to-case thermal resistance (the case is actually the top of the exposed silicon die) ? the die junction-to-board thermal resistance figure 60 depicts the primary heat transfer path for a pa ckage with an attached heat sink mounted to a printed-circuit board. figure 60. c4 package with heat sink mounted to a printed-circuit board external resistance external resistance internal resistance radiation convection radiation convection heat sink printed-circuit board thermal interface material package/leads die junction die/package (note the internal versus external package resistance.)
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 freescale semiconductor 111 thermal heat generated on the active side of the chip is c onducted through the silicon, then the heat sink attach material (or thermal interface material), and finally to the heat sink where it is removed by forced-air convection. because the silicon thermal resistance is quite small, the temperature drop in the silicon may be neglected for a first-order analysis. thus the thermal inte rface material and the heat sink conduction/convective thermal resistances are the dominant terms. 19.2.2 thermal interface materials a thermal interface material is recommended at the package-to-heat sink interface to minimize the thermal contact resistance. figure 61 shows the thermal performance of three thin-sheet thermal-interface materials (silicone, graphite/oil, floroether oil), a bare joint, and a joint with thermal grease as a function of contact pressure. as shown, the performance of these thermal interface materials improves with increasing contact pressure. the use of thermal grease significantly reduces the interface thermal resistance. that is, the bare joint results in a thermal resistance approximately seven times greater than the thermal grease joint. often, heat sinks are attached to the package by means of a spring clip to holes in the printed-circuit board (see figure 59 ). therefore, synthetic grease offers the best thermal performance, considering the low interface pressure, and is recommended due to the high power dissipation of the mpc8640. of course, the selection of any thermal interface material depends on many factors?thermal performance requirements, manufacturability, service temperature, dielectric properties, cost, and so on. figure 61. thermal performance of select thermal interface material 0 0.5 1 1.5 2 0 1020304050607080 silicone sheet (0.006 in.) bare joint fluoroether oil sheet (0.007 in.) graphite/oil sheet (0.005 in.) synthetic grease contact pressure (psi) specific thermal resistance (k-in. 2 /w)
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 112 freescale semiconductor thermal the board designer can choose between several types of thermal interface. heat sink adhesive materials should be selected based on high conductivity and mechan ical strength to meet equipment shock/vibration requirements. there are several commercially available thermal interfaces and adhesive materials provided by the following vendors: the bergquist company 800-347-4572 18930 west 78 th st. chanhassen, mn 55317 internet: www.bergquistcompany.com chomerics, inc. 781-935-4850 77 dragon ct. woburn, ma 01801 internet: www.chomerics.com dow-corning corporation 800-248-2481 corporate center po box 994 midland, mi 48686-0994 internet: www.dowcorning.com shin-etsu microsi, inc. 888-642-7674 10028 s. 51st st. phoenix, az 85044 internet: www.microsi.com thermagon inc. 888-246-9050 4707 detroit ave. cleveland, oh 44102 internet: www.thermagon.com the following section provides a heat sink selection ex ample using one of the commercially available heat sinks. 19.2.3 heat sink selection example for preliminary heat sink sizing, the die-junction temperature can be expressed as follows: t j = t i + t r + (r jc + r int + r sa ) p d where: t j is the die-junction temperature t i is the inlet cabinet ambient temperature t r is the air temperature rise within the computer cabinet r jc is the junction-to-case thermal resistance r int is the adhesive or interface material thermal resistance r sa is the heat sink base-to-ambient thermal resistance p d is the power dissipated by the device
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 freescale semiconductor 113 thermal during operation, the die-junction temperatures (t j ) should be maintained less than the value specified in table 2 . the temperature of air cooling the component gr eatly depends on the ambient inlet air temperature and the air temperature rise within the electronic cabinet. an electronic cabinet inlet-air temperature (t i ) may range from 30 to 40 c. the air temperature rise within a cabinet (t r ) may be in the range of 5to10 c. the thermal resistance of the thermal interface material (r int ) is typically about 0.2 c/w. for example, assuming a t i of 30 c, a t r of 5 c, a package r jc = 0.1, and a typical power consumption (p d ) of 43.4 w, the following expression for t j is obtained: die-junction temperature: t j = 30 c + 5 c + (0.1 c/w + 0.2 c/w + sa ) 43.4 w for this example, a r sa value of 1.32 c/w or less is required to maintain the die junction temperature below the maximum value of table 2 . though the die junction-to-ambient and the heat si nk-to-ambient thermal resistances are a common figure-of-merit used for comparing the thermal performance of various microelectronic packaging technologies, one should exercise cauti on when only using this metric in determining thermal management because no single parameter can adequately describe three-dimensional heat flow. the final die-junction operating temperature is not only a function of th e component-level thermal resistance, but the system-level design and its operating conditions. in addition to the component's power consumption, a number of factors affect the final operating die-j unction temperature?airflow, board population (local heat flux of adjacent components), heat sink efficiency, heat sink pl acement, next-level interconnect technology, system air temperature rise, altitude, and so on. due to the complexity and variety of system-level boundary conditions for today's microelectronic equipment, the combined effects of the heat transf er mechanisms (radiation, convection, and conduction) may vary widely. for these reasons, we recommend using conjugate heat transfer models for the board as well as system-level designs. for system thermal modeling, the mpc8640 thermal model is shown in figure 62 . four cuboids are used to represent this device. the die is modeled as 12.4 15.3 mm at a thickness of 0.86 mm. see section 3, ?power characteristics,? for power dissipation details. the substrate is modeled as a single block 33 33 1.2 mm with orthotropic conductivity: 13.5 w/(m ? k) in the xy-plane and 5.3 w/(m ? k) in the z-direction. the die is centered on the substrate. the bump/underfill layer is modeled as a collapsed thermal resistance between the die and substrate with a conductivity of 5.3 w/(m ? k) in the thickness dimension of 0.07 mm. because the bump/underfill is m odeled with zero physical dimension (collapsed height), the die thickness was slightly enlarged to provide the correct height. the c5 solder layer is modeled as a cuboid with dimensions 33x33x0.4 mm a nd orthotropic thermal conductivity of 0.034 w/(m ? k) in the xy-plane and 9.6 w/(m ? k) in the z-direction. an lga solder layer would be modeled as a collapsed thermal resistance with th ermal conductivity of 9.6w/(m ? k) a nd an effective height of 0.1 mm.
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 114 freescale semiconductor thermal the thermal model uses approximate dimensions to reduce grid. please refer to the case outline for actual dimensions. figure 62. recommended thermal model of mpc8640 19.2.4 temperature diode the mpc8640 has a temperature diode on the microproces sor that can be used in conjunction with other system temperature monitoring devices (such as analog devices, adt7461?). these devices use the negative temperature coefficient of a diode operated at a constant current to determine the temperature of the microprocessor and its environment. for proper operation, the monitoring device used should auto-calibrate the device by canceling out the v be variation of each mpc8640?s internal diode. the following are the specifications of the mpc8640 on-board temperature diode: v f > 0.40 v v f < 0.90 v operating range 2?300 a diode leakage < 10 na at 125 c ideality factor over 5?150 a at 60 c: n = 1.0275 0.9% bump and underfill die substrate c5 solder layer die substrate side view of model (not to scale) top view of model (not to scale) x y z conductivity value unit die (12.4 15.3 0.86 mm) silicon temperature dependent bump and underfill (12.4 15.3 0.07 mm) collapsed resistance k z 5.3 w/(m ? k) substrate (33 33 1.2 mm) k x 13.5 w/(m ? k) k y 13.5 k z 5.3 c5 solder layer (33 33 0.4 mm) k x 0.034 w/(m ? k) k y 0.034 k z 9.6
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 freescale semiconductor 115 thermal ideality factor is defined as the de viation from the ideal diode equation: another useful equation is: where: i fw = forward current i s = saturation current v d = voltage at diode v f = voltage forward biased v h = diode voltage while i h is flowing v l = diode voltage while i l is flowing i h = larger diode bias current i l = smaller diode bias current q = charge of electron (1.6 x 10 ?19 c) n = ideality factor (normally 1.0) k = boltzman?s constant (1.38 x 10 ?23 joules/k) t = temperature (kelvins) the ratio of i h to i l is usually selected to be 10:1. the above simplifies to the following: solving for t, the equation becomes: i fw = i s e ? 1 qv f ___ nkt v h ? v l = n ln kt __ q i h __ i l v h ? v l = 1.986 10 ?4 nt nt = v h ? v l __________ 1.986 10 ?4
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 116 freescale semiconductor system design information 20 system design information this section provides electrical and thermal design recommendations for successful application of the mpc8640. 20.1 system clocking this device includes six plls, as follows: ? the platform pll generates the platform clock from the externally supplied sysclk input. the frequency ratio between the platform and sysclk is selected using the platform pll ratio configuration bits as described in section 18.2, ?mpx to sysclk pll ratio.? ? the dual e600 core plls generate the e 600 clock from the externally supplied input. ? the local bus pll generates the clock for the local bus. ? there are two internal plls for the serdes block. 20.2 power supply design and sequencing this section describes the power supply design and sequencing. 20.2.1 pll power supply filtering each of the plls listed in section 20.1, ?system clocking,? is provided with power through independent power supply pins. there are a number of ways to reliably provide power to the plls, but the recommended solution is to provide independent filter circuits pe r pll power supply as illustrated in figure 64 , one to each of the av dd type pins. by providing independent filters to each pll the opportunity to cause noise injection from one pll to the other is reduced. this circuit is intended to filter noise in the p lls resonant frequency range from a 500 khz to 10 mhz range. it should be built with surface mount capacitor s with minimum effective series inductance (esl). consistent with the recommendations of dr. howard johnson in high speed digital design: a handbook of black magic (prentice hall, 1993), multiple small capacito rs of equal value are recommended over a single large value capacitor. each circuit should be placed as close as possible to the specific av dd type pin being supplied to minimize noise coupled from nearby circuits. it should be possible to route directly from the capacitors to the av dd type pin, which is on the periphery of the footprint, without the inductance of vias. figure 63 and figure 64 show the pll power supply filter circuits for the platform and cores, respectively. figure 63. mpc8640 pll power supply filter circuit (for platform and local bus) 2.2 f 2.2 f gnd low esl surface mount capacitors 10 av dd _plat, av dd _lb; v dd _plat
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 freescale semiconductor 117 system design information figure 64. mpc8640 pll power supply filter circuit (for cores) the av dd _srds n signals provide power for the analog portions of the serdes pll. to ensure stability of the internal clock, the power supplied to the pll is filtered using a circuit similar to the one shown in following figure. for maximum effectiveness, the filter circuit is placed as closely as possible to the av dd _srds n balls to ensure it filters out as much noise as possible. the ground connection should be near the av dd _srds n balls. the 0.003-f capacitor is closest to the balls, followed by the two 2.2-f capacitors, and finally the 1- resistor to the board supply plane. the capacitors are connected from av dd _srds n to the ground plane. use ceramic chip capacitors with the highest possible self-resonant frequency. all traces should be kept short, wide, and direct. figure 65. serdes pll power supply filter note the following: ?av dd _srds n should be a filtered version of sv dd . ? signals on the serdes interface are fed from the sv dd power plan. 20.2.2 pll power supply sequencing for details on power sequencing for the av dd type and supplies refer to section 2.2, ?power-up/down sequence.? 20.3 decoupling recommendations due to large address and data buses, and high operati ng frequencies, the device can generate transient power surges and high frequency noise in its power suppl y, especially while driving large capacitive loads. this noise must be prevented from reaching other components in the mpc8640 system, and the device itself requires a clean, tightly regulated source of power. therefore, it is recommended that the system v dd _core0/1 av dd _core0/1 2.2 f 2.2 f gnd low esl surface mount capacitors 10 filter circuit (should not be used for single core device) note: for single core device the filter circuit (in the dashed box) should be removed and av dd _core1 should be tied to ground with a weak (2?10 k ) pull-down resistor. 2.2 f 1 0.003 f gnd 1.0 av dd _srds n 1. an 0805 sized capacitor is recommended for system initial bring-up. sv dd 2.2 f 1
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 118 freescale semiconductor system design information designer place at least one decoupling capacitor at each ov dd , d n _gv dd , lv dd , tv dd , v dd _core n , and v dd _plat pin of the device. these decoupling capacito rs should receive their power from separate ov dd , d n _gv dd , lv dd , tv dd , v dd _core n , and v dd _plat and gnd power planes in the pcb, utilizing short traces to minimize inductance. capac itors may be placed directly under the device using a standard escape pattern. ot hers may surround the part. these capacitors should have a value of 0.01 or 0.1 f. only ceramic smt (surface mount technology) capacitors should be used to minimize lead inductance, preferably 0402 or 0603 sizes. in addition, it is recommended that there be several bulk storage capacitors distributed around the pcb, feeding the ov dd , d n _gv dd , lv dd , tv dd , v dd _core n , and v dd _plat planes, to enable quick recharging of the smaller chip capacitors. they should also be connected to the power and ground planes through two vias to minimize inductance. sugge sted bulk capacitors?100?330 f (avx tps tantalum or sanyo oscon). 20.4 serdes block power supply decoupling recommendations the serdes block requires a clean, tightly regulated source of power (sv dd and xv dd _srds n ) to ensure low jitter on transmit and reliable recovery of data in the receiver. an appropria te decoupling scheme is outlined below. only surface mount technology (smt) capacitors shoul d be used to minimize inductance. connections from all capacitors to power and ground should be done with multiple vias to further reduce inductance. ? first, the board should have at least 10 10-nf smt ceramic chip capacitors as close as possible to the supply balls of the device. where the board has blind vias, these capacitors should be placed directly below the chip supply and ground connecti ons. where the board does not have blind vias, these capacitors should be placed in a ring around the device as close to the supply and ground connections as possible. ? second, there should be a 1-f ceramic chip capac itor on each side of the device. this should be done for all serdes supplies. ? third, between the device and any serdes voltage regulator there should be a 10-f, low equivalent series resistance (esr) smt tantalum chip capacitor and a 100-f, low esr smt tantalum chip capacitor. this shoul d be done for all serdes supplies. 20.5 connection recommendations to ensure reliable operation, it is highly recommende d to connect unused inputs to an appropriate signal level. in general all unused active low inputs should be tied to ov dd , d n _gv dd , lv dd , tv dd , v dd _core n , and v dd _plat, xv dd _srds n , and sv dd as required and unused active high inputs should be connected to gnd. all nc (no-connect) signals must remain unconnected. the following list explains the special cases: ? ddr?if one of the ddr ports is not being used the power supply pins for that port can be connected to ground so that there is no need to c onnect the individual unused inputs of that port to ground. note that these power supplies can only be powered up again at reset for functionality to occur on the ddr port. power supplies for other functional buses should remain powered.
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 freescale semiconductor 119 system design information ? local bus?if parity is not used, tie ldp[0:3] to ground via a 4.7-k resistor, tie lpbse to ov dd via a 4.7-k resistor (pull-up resistor). for systems which boot from local bus (gpcm)-controlled flash, a pull-up on lgpl4 is required. ? serdes?receiver lanes configured for pci express are allowed to be disconnected (as would occur when a pci express slot is connected but not populated). directions for terminating the serdes signals is discussed in section 20.5.1, ?guidelines for high-speed interface termination .? 20.5.1 guidelines for high-speed interface termination this section provides the guidelines for high-speed interface termination. 20.5.1.1 serdes interface the high-speed serdes interface can be disabled through the por input cfg_io_ports[0:3] and through the devdisr register in software. if a serdes port is disabled through the por input the user cannot enable it through the devdisr register in software. however, if a serdes port is enabled through the por input the user can disable it through the devdisr register in software. disabling a serdes port through software should be done on a temporary basis. power is always required for the serdes interface, even if the port is disabled through either mechanism. table 72 describes the possible enabled/disabled scenarios for a serdes port. the termination recommendations must be followed for each port. if the high-speed serdes port requires complete or partial termination, the unused pins should be terminated as described in this section. table 72. serdes port enabled/disabled configurations disabled through por input enabled through por input enabled through devdisr serdes port is disabled (and cannot be enabled through devdisr) complete termination required (reference clock not required) serdes port is enabled partial termination may be required 1 (reference clock is required) 1 partial termination when a serdes port is enabled through both por input and devdisr is determined by the serdes port mode. if the port is in 8 pci express mode, no termination is required because all pins are being used. if the port is in 1/ 2/ 4 pci express mode, termination is required on the unused pins. if the port is in 4 serial rapidio mode, termination is required on the unused pins. disabled through devdisr serdes port is disabled (through por input) complete termination required (reference clock not required) serdes port is disabled after software disables port same termination requirements as when the port is enabled through por input 2 (reference clock is required) 2 if a serdes port is enabled through the por input and then disabled through devdisr, no hardware changes are required. termination of the serdes port should follow what is required when the port is enabled through both por input and devdisr. see note 1 for more information. note:
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 120 freescale semiconductor system design information the following pins must be left unconnected (floating): ?sd n _tx[7:0] ?sd n _tx [7:0] the following pins must be connected to gnd: ?sd n _rx[7:0] ?sd n _rx [7:0] ?sd n _ref_clk ? sd n _ref_clk note it is recommended to power down the unused lane through srds1cr1[0:7] register (offset = 0xe_0f08) and srds2cr1[0:7] register (offset = 0xe_0f44.) (this prevents the oscillations and holds the receiver output in a fixed state.) that maps to serdes lane 0 to lane 7 accordingly. for other directions on reserved or no-connects pins see section 17, ?signal listings .? 20.6 pull-up and pull-down resistor requirements the mpc8640 requires weak pull-up resistors (2?10 k is recommended) on all open drain type pins. the following pins must not be pulled down during power-on reset: tsec4_txd[4], lgpl0/lsda10, lgpl1/lsdwe , trig_out/ready, and d1_msrcid[2]. the following are factory test pins and require strong pull-up resistors (100 ?1 k ) to ov dd lssd_mode , test_mode[0:3].the following pins require weak pull-up resistors (2?10 k ) to their specific power supplies : lcs [0:4], lcs [5]/dma_dreq 2, lcs [6]/dma_dack [2], lcs [7]/dma_ddone [2], irq_out, iic1_sda, iic1_scl, iic2_sda, iic2_scl, and ckstp_out . the following pins should be pulled to ground with a 100- resistor: sd1_imp_cal_tx, sd2_imp_cal_tx. the following pins should be pulled to ground with a 200- resistor: sd1_imp_cal_rx, sd2_imp_cal_rx tsec n _tx_en signals require an external 4.7-k pull down resistor to prevent phy from seeing a valid transmit enable before it is actively driven. when the platform frequency is 400 mhz, tsec1_txd[1] must be pulled down at reset. tsec2_txd[4] and tsec2_tx_er pins function as cfg_dram_type[0 or 1] at reset and must be valid before hreset assertion when coming out of device sleep mode. 20.6.1 special instructions for single core device the mechanical drawing for the single core device does not have all the solder balls that exist on the single core device. this includes all the balls for vdd_core1 and sensev dd _core1 which exist on the package for the dual core device, but not on the single core package. a solder ball is present for
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 freescale semiconductor 121 system design information sensev ss _core1 and needs to be connected to ground with a weak (2?10 k ) pull down resistor. likewise, av dd _core1 needs to be pulled to ground as shown in figure 64 . the mechanical drawing for the single core device is located in section 16.2, ?mechanical dimensions of the mpc8640 fc-cbga .? for other pin pull-up or pull-down recommendations of signals, please see section 17, ?signal listings .? 20.7 output buffer dc impedance the mpc8640 drivers are characterized over process, voltage, and temperature. for all buses, the driver is a push-pull single-ended driver type (open drain for i 2 c). to measure z 0 for the single-ended drivers, an external resistor is connected from the chip pad to ov dd or gnd. then, the value of each resistor is varied until the pad voltage is ov dd /2 (see figure 66 ). the output impedance is the average of two components, the resistances of the pull-up and pull-down devices. when data is held high, sw1 is closed (sw2 is open) and r p is trimmed until the voltage at the pad equals ov dd /2. r p then becomes the resistance of the pull-up devices. r p and r n are designed to be close to each other in value. then, z 0 = (r p + r n ) 2. figure 66. driver impedance measurement table 73 summarizes the signal impedance targets. the driver impedances are targeted at minimum v dd , nominal ov dd , 105 c. table 73. impedance characteristics impedance duart, control, configuration, power management pci express ddr dram symbol unit r n 43 target 25 target 20 target z 0 w r p 43 target 25 target 20 target z 0 w note: nominal supply voltages. see ta b l e 1 , t j = 105 c. ov dd ognd r p r n pad data sw1 sw2
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 122 freescale semiconductor system design information 20.8 configuration pin muxing the mpc8640 provides the user with power-on configuration options which can be set through the use of external pull-up or pull-down resistors of 4.7 k on certain output pins (see cu stomer visible configuration pins). these pins are generally used as output only pins in normal operation. while hreset is asserted however, these pins are treated as inputs. the value presented on these pins while hreset is asserted, is latched when hreset deasserts, at which time the input receiver is disabled and the i/o circuit takes on its normal function. most of these sampled configuration pins are equipped with an on-chip gated resi stor of approximately 20 k . this value should permit the 4.7-k resistor to pull the configuration pin to a valid logic low level. the pull-up resistor is enabled only during hreset (and for platform/system clocks after hreset deassertion to ensure capture of the reset value). when the input receiver is disabled, the pull-up is also, thus allo wing functional operation of the pin as an output with minimal signal quality or delay disruption. the default va lue for all configuration bits treated this way has been encoded such that a high voltage level puts the de vice into the default state and external resistors are needed only when non-default settings are required by the user. careful board layout with stubless connections to th ese pull-down resistors coupled with the large value of the pull-down resistor should minimize the disruption of signal quality or speed for output pins thus configured. the platform pll ratio and e600 pll ratio configura tion pins are not equipped with these default pull-up devices. 20.9 jtag configuration signals correct operation of the jtag interface requires configuration of a group of system control pins as demonstrated in figure 68 . care must be taken to ensure that these pins are maintained at a valid deasserted state under normal operating conditions as most have asynchronous behavior and spurious assertion will give unpredictable results. boundary-scan testing is enabled through the jtag interface signals. the trst signal is optional in the ieee 1149.1 specification, but is provided on all processors that implement the power architecture technology. the device requires trst to be asserted during reset conditions to ensure the jtag boundary logic does not interfere with normal chip operation. while it is possible to force the tap controller to the reset state using only the tck and tms signals, more reliable power-on reset performance will be obtained if the trst signal is asserted during power-on reset. because the jtag interface is also used for accessing the common on-chip processor (cop) function, simply tying trst to hreset is not practical. the cop function of these processors allows a remote computer system (typically a pc with dedicated hardware and debugging software) to access and control the internal operations of the processor. the cop port connects primarily through the jtag interface of the processor, with some additional status monitoring signals. the cop port requires the ability to independently assert hreset or trst in order to fully control the processor. if the target system ha s independent reset sources, such as voltage monitors, watchdog timers, power supply failures, or push-button switches, then the cop reset signals must be merged into these signals with logic. the arrangement shown in figure 67 allows the cop port to independently assert hreset or trst , while ensuring that the target can drive hreset as well.
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 freescale semiconductor 123 system design information the cop interface has a standard header, shown in figure 67 , for connection to the target system, and is based on the 0.025" square-post, 0.100" centered header assembly (often called a berg header). the connector typically has pin 14 removed as a connector key. the cop header adds many benefits such as breakpoints, watchpoints, register and memory examination/modification, and othe r standard debugger features. an inexpensive option can be to leave the cop header unpopulated until needed. there is no standardized way to number the cop header shown in figure 67 ; consequently, many different pin numbers have been observed from emulator vendors. some are numbered top-to-bottom then left-to-right, while others use left-to-right then top- to-bottom, while still others number the pins counter clockwise from pin 1 (as with an ic). regardless of the numbering, the signal placement recommended in figure 67 is common to all known emulators. for a multi-processor non-daisy chain configuration, figure 68 , can be duplicated for each processor. the recommended daisy chain configuration is shown in figure 69 . please consult with your tool vendor to determine which configuration is supported by their emulator. 20.9.1 termination of unused signals if the jtag interface and cop header will not be used, freescale recommends the following connections: ?trst should be tied to hreset through a 0 k isolation resistor so that it is asserted when the system reset signal (hreset ) is asserted, ensuring that the jtag scan chain is initialized during the power-on reset flow. freescale recommends that the cop header be designed into the system as shown in figure 68 . if this is not possible, the isolation resistor will allow future access to trst in case a jtag interface may need to be wired onto the system in future debug situations. ? tie tck to ov dd through a 10 k resistor. this will prevent tck from changing state and reading incorrect data into the device. ? no connection is required for tdi, tms, or tdo. figure 67. cop connector physical pinout 3 13 9 5 1 6 10 15 11 7 16 12 8 4 key no pin 1 2 cop_tdo cop_tdi nc nc cop_trst cop_vdd_sense cop_chkstp_in nc nc gnd cop_tck cop_tms cop_sreset cop_hreset cop_chkstp_out
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 124 freescale semiconductor system design information figure 68. jtag/cop interface connection for one mpc8640 device hreset from target board sources cop_hreset 13 cop_sreset sreset 1 nc 11 cop_vdd_sense 2 6 5 15 10 10 k 10 k cop_chkstp_in ckstp_in 8 cop_tms cop_tdo cop_tdi cop_tck tms tdo tdi 9 1 3 4 cop_trst 7 16 2 10 12 (if any) cop header 14 3 3. the key location (pin 14) is not physically present on the cop header. 10 k trst 1 10 k 10 k 10 k ckstp_out cop_chkstp_out 3 13 9 5 1 6 10 15 11 7 16 12 8 4 key no pin cop connector physical pinout 1 2 nc srese t1 nc ov dd 10 k 10 k hreset 1 4. although pin 12 is defined as a no-connect, some debug tools may use pin 12 as an additional gnd pin for improved signal integrity. tck 4 5 5. this switch is included as a precaution for bsdl testing. the switch should be open during bsdl testing to avoid accidentally asserting the trst line. if bsdl testing is not being performed, this switch should be closed or removed. 10 k sreset 0 10 k srese t0 2. populate this with a 10 resistor for short-circuit/current-limiting protection. 1. the cop port and target board should be able to independently assert hreset and trst to the processor in order to fully control the processor as shown here. notes:
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 freescale semiconductor 125 system design information figure 69. jtag/cop interface connection for multiple mpc8640 devices in daisy chain configuration cop_sreset cop_trst cop_hreset jtag/cop sreset1 sreset0 tdi header hreset trst chkstp_out chkstp_in tms tck tdo 10k 10k sreset1 hreset from target board sources (if any) cop_tdi 11 13 3 cop_chkstp_out cop_chkstp_in sreset1 sreset0 tdi trst chkstp_out chkstp_in tms tck tdo 4 15 8 cop_tms 2 10 cop_tck gnd 14 9 7 6 nc nc cop_vdd_sense 16 cop_tdo 1 3 12 2 hreset ov dd sreset0 4 4 4 4 10 k notes: 1. populate this with a 10- resistor for short circuit/current-limiting protection. 2. key location; pin 14 is not physically present on the cop header. 3. use a and gate with sufficient drive strength to drive two inputs. 4. the cop port and target board should be able to independently assert hreset and trst to the processor in order to fully control the processor as shown above. 10k 10k 10k 10k 10k 10k 10k 6 5 10 mpc8640 mpc8640 3 5. this switch is included as a precaution for bsdl testing. the switch should be open during bsdl testing to avoid accidentally asserting the trst line. if bsdl testing is not being performed, this switch should be closed or removed. 6. although pin 12 is defined as a no-connect, some debug tools may use pin 12 as an additional gnd pin for improved signal integrity. 5 nc 1 ov dd
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 126 freescale semiconductor ordering information 21 ordering information ordering information for the parts fully covered by this specification document is provided in section 21.1, ?part numbers fully addressed by this document.? 21.1 part numbers fully addressed by this document table 74 provides the freescale part numbering nomenclatur e for the mpc8640. note that the individual part numbers correspond to a maximum processor core frequency. for available fr equencies, contact your local freescale sales office. in addition to the processor frequency, the part numbering scheme also includes an application modifier which may specify sp ecial application conditions. each part number also contains a revision code which refers to the die mask revision number. table 74. part numbering nomenclature uu nnnn d w xx yyyy a z product code part identifier core count temp package 1 core processor frequency 2 (mhz) ddr speed (mhz) product revision level mc 5 8640 blank = single core blank: 0 c to 105 c t: ?40 c to 105 c hx = high-lead hcte fc-cbga vu = rohs lead-f ree hcte fc-cbga 1000, 1067, 1250 n = 533 mhz 4 h = 500 mhz revision c = 2.1 system version register value for rev c: 0x8090_0021 mpc8640 0x8090_0121 mpc8640d revision e = 3.0 system version register value for rev e: 0x8090_0030 mpc8640 0x8090_0130 mpc8640d d = dual core notes: 1. see section 16, ?package,? for more information on available package types. 2. processor core frequencies supported by parts addressed by this specification only. not all parts described in this specifica tion support all core frequencies. additionally, parts addressed by part number specifications may support other maximum core frequencies. 3. the p prefix in a freescale part number designates a ?pilot production prototype? as defined by freescale sop 3-13. these par ts have only preliminary reliability and characterization data. before pilot production prototypes may be shipped, written authorization from the customer must be on file in the applicable sales office acknowledging the qualification status and the f act that product changes may still occur while shipping pilot production prototypes. 4. part number mc8640xxx1067nz is our low v dd _core n device. v dd _core n = 0.95 v and v dd _plat = 1.05 v. 5. mc - qualified production
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 freescale semiconductor 127 ordering information table 75 shows the parts that are available fo r ordering and their operating conditions. table 75. part offerings and operating conditions part offerings 1 1 note that the ?w? represents the operating temperature range. the ?xx? in the part marking represents the package option. the ?z? represents the product revision level. for more information see ta b l e 7 4 . operating conditions mc8640dwxx1250hz dual core max cpu speed = 1250 mhz, max ddr = 500 mhz core voltage = 1.05 volts mc8640dwxx1000hz dual core max cpu speed = 1000 mhz, max ddr = 500 mhz core voltage = 1.05 volts mc8640dwxx1067nz dual core max cpu speed = 1067 mhz, max ddr = 533 mhz core voltage = 0.95 volts mc8640wxx1250hz single core max cpu speed = 1250 mhz, max ddr = 500 mhz core voltage = 1.05 volts mc8640wxx1000hz single core max cpu speed = 1000 mhz, max ddr = 500 mhz core voltage = 1.05 volts mc8640wxx1067nz single core max cpu speed = 1067 mhz, max ddr = 533 mhz core voltage = 0.95 volts
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 128 freescale semiconductor document revision history 21.2 part marking parts are marked as the example shown in figure 70 . figure 70. part marking for fc-cbga device 22 document revision history table 76 provides a revision history for the mpc8640d hardware specification. table 76. document revision history revision date substantive change(s) 3 07/2009 ? updated ta b l e 7 4 , ?part numbering nomenclature,? and ta b l e 7 5 , ?part offerings and operating conditions,? to include silicon revision 3.0 part markings. 2 06/2009 ? added tab le 5 , ?mpc8640d individual supply maximum power dissipation 1.? ? added note 8 to ta b l e 4 9 , ?differential transmitter output specifications.? mc8640x xxnnnnxx twlyyww mmmmmm ywwlaz ywwlaz is the assembly traceability code. mmmmmm is the m00 (mask) number. twlyyww is the test code note: 8640d
mpc8640 and mpc8640d integrated host processor hardware specifications, rev. 3 freescale semiconductor 129 document revision history 1 11/2008 ? removed voltage option of 1.10 v from ta b l e 2 because it is not supported by mpc8640d or mpc8640 ? updated tab le 4 and ta b l e 6 with the new 1067/533 mhz device offering. this includes updated power specifications. ? added section 4.4, ?platform frequency requirements for pci-express and serial rapidio ? ? updated section 6, ?ddr and ddr2 sdram ? to include 533 mhz. ? added core frequency of 1067 to ta ble 6 4 , ta b l e 6 5 , ta b l e 6 6 and ta b l e 6 7 ? changed max memory clock frequency from 250 mhz to 266 mhz in ta b l e 6 5 ? changed max mpx/platform clock frequency from 500 mhz to 533 mhz in ta b l e 6 6 ? changed max local bus clock speed from 1 mhz to 133 mhz in ta b l e 6 7 ? added mpx:sysclk ratio of 8:1 to ta b l e 6 8 ? added core:mpx ratio of 3:1 to ta b l e 6 9 ? updated ta b l e 7 0 to include 533 mpx clock frequency ? changed the extended temp range part numbering ?w? to be t instead of an h in ta ble 7 4 ? changed the ddr speed part numbering n to stand for 533 mhz instead of 500 mhz in tab le 7 4 ? removed the statement ?note that core processor speed of 1500 mhz is only available for the mpc8640d (dual core)? from note 2 in table 74 because mpc8640d is not offered at 1500 mhz core. ? removed the part offering mc8640dwxx1000nc which is replaced with mc8640dwxx1067nc and removed mc8640wxx1000nc replaced with mc8640wxx1067nc in ta ble 7 5 ? added note 8 to figure 57 and figure 58 . 0 07/2008 ? initial release table 76. document revision history revision date substantive change(s)
document number: mpc8640dec rev. 3 07/2009 information in this document is provided solely to enable system and software implementers to use freescale semiconductor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters which may be provided in freescale semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor, inc. technical information center, el516 2100 east elliot road tempe, arizona 85284 1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor china ltd. exchange building 23f no. 118 jianguo road chaoyang district beijing 100022 china +86 10 5879 8000 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center 1-800 441-2447 or +1-303-675-2140 fax: +1-303-675-2150 ldcforfreescalesemiconductor @hibbertgroup.com freescale and the freescale logo are trademarks or registered trademarks of freescale semiconductor, inc. in the u.s. and other countries. all other product or service names are the property of their respective owners. the power architecture and power.org word marks and the power and power.org logos and related marks are trademarks and service marks licensed by power.org. ieee 802.3, 802.3u, 802.3x, 802.3z, 802.3ac, 802.3ab, and 1149.1 are registered trademarks of the institute of electrical and electronics engineers, inc. (ieee). this product is not endorsed or approved by the ieee. ? freescale semiconductor, inc., 2009. all rights reserved.

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